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SiFive's Computers

A project log for Kestrel Computer Project

The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.

Samuel A. Falvo IISamuel A. Falvo II 07/26/2016 at 00:450 Comments

I'm going to be blunt. Sifive released a bunch of computer designs around their U500 and E300 RISC-V cores. Should I even bother continuing with the Kestrel project? Does anyone even care?

So, Sifive, Inc. released a handful of development platforms, both of which have FPGA bitstreams available which turns them into full-blown computers. It is said that the platform specification for these are available to the public under open license terms (presumably also BSD licensed, as the RISC-V ISA itself is). The Freedom platform can be had for a paltry $3500 (after rounding up to two significant digits); however, the lower-level Everywhere platform can be had for $130-ish. Before taxes and shipping, of course.

On the one hand, I'm quite happy that these alternatives exist. RISC-V needed a standard development platform for some time now. However, I also feel kind of betrayed a little bit. I mean, I've been working on Kestrel for years now. My project was not a secret; and, nobody thought to contribute.

Nobody.

Not one person from anywhere else in the RISC-V community.

Now that two options exist for RISC-V computing which out-classes the Kestrel in every benchmark you can think of, I just want to gauge who is really interested in the Kestrel now.

And, I'm not talking about the kind of interest that involves lurkers who watch over my shoulder just to monitor progress. Not that there's anything wrong with such folks; it's how some people learn, and let's face it, we've all been there at one point in our lives. I've answered many questions from such folks, and I enjoy the technical discussions that this brings up.

I'm talking about folks who are interested in the Kestrel for its own sake: those who are interested enough to want to own one for themselves, who motivated me to bring my project to this very site even. I'm talking about the folks who expressed to my directly that they wanted to purchase a supported FPGA dev board and program them with a bitstream from me, or who wanted a kit made available on Tindie or something. Remember what you would get though:

At no time did I give any illusions about what the Kestrel-3 platform would entail coming out of the gate. I clearly described its CPU as a kind of 64-bit 6502-like CPU, while I described the computer as a whole as roughly matching an Amiga 500 or Atari ST 520 in execution performance. Future revisions of the platform were to bring enhanced performance or capability; e.g., faster CPU to deliver closer to 80 MIPS performance until dedicated silicon came out, RapidIO-inspired (if not -compatible) interconnects, etc. The goal was to incrementally evolve the design to something that would be truly useable on the desktop.

If nobody has any interest in it, then I will just cancel the Backbone development project and not bother putting up a Kestrel kit on Tindie or wherever; I'll just stick with my Digilent Nexys 2, maybe acquire another FPGA board in the future and make it run there as well (since the Nexys 2 isn't sold anymore). I'll just focus on developing the Kestrel for myself by myself (which is how the project started to begin with, and continues to operate), which implies my documentation efforts (the Kestrel-3 User's Guide, for instance) will basically come to a stand-still. I'll forego any ambition to ever run BSD or Linux on it, I'll just keep it running Forth, Oberon (eventually), and/or perhaps a port of Shen OS (where OS == Open Source, in this case. Shen is not an operating system). The CPU will likely remain at 6 MIPS performance until I grow tired of it, but I seriously doubt it'll exceed 20 MIPS long term, as it will probably remain a soft-core CPU for a long, long time. The Kestrel-3 platform is definitely incompatible with the Sifive platform specification as both stand, so don't expect binary interop with that computer. We're talking about computers that are as different from one another as an S-100 bus based computer is from a TRS-80 model I.

If people do express an interest, though, things will change slightly. First and foremost, I'll design the video and other cores with upward mobility features; by which, I mean, future support for eventual design goals like the use of SDRAM instead of asynchronous RAM. (You'll be amazed at how much this changes the ideal register set.) I will research the use of RapidIO or comparable interconnect technologies when the time is right. After the initial CPU is released, I have plans for adding user- and supervisor-modes to it, so that memory protection features can be incorporated into the design. This would allow it to run Linux, if someone (not me) decided to port it. Plan 9 from Bell Labs was on the table as of last year, for instance.

So, let me know what you think I should do. This may well be the last time I ask this question.

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