Over the weekend, I spent time in LibreCalc to create a set of instruction decoder "PLA" minterms and the desired output enables they imply. I'm only missing CSRR* instructions at this point, but hopefully I can get those implemented soon. These are still in "human" form; I still need to spend the time translating them into equivalent Verilog codes.

I haven't quite figured out how to get CSRs to work in the new microarchitecture yet. I think I can make all CSR instructions run in 4 cycles, same as any other ALU-based instruction. However, CSR instructions are more "complicated"; not nearly as RISCy as I'd like them to be. Every one involves either an exchange or some bit-level mutilation of various fields. For example, CSRRC is equivalent to DEST = CSR{n]; CSR[n] = CSR[n] AND NOT SRC. It's rather annoying, frankly, and it will involve creating a whole new set of buses and consuming resources. Not only that, but unrecognized CSRs need to cause illegal instruction traps, which means I have no choice but to recognize this condition in the first cycle. So, CSR decoding must be fast, and that means it will not generally be optimized for small size.

On the emulator front, I've started to update the "e" Kestrel emulator to use the new Privileged ISA 1.9 specification. I'm rather surprised that eForth still boots without any changes so far. I'm sure I'll need to fix something once everything is settled in though, but as of right now, the new machine-mode semantics seems to be behaving exactly as one would expect.

One change which I know will cause breakage is the old ERET instruction. The bit pattern for ERET matches the new SRET instruction (return from supervisor mode, not the V1.7 "system return" instruction). Since I will not be implementing S-mode, SRET will have to cause an illegal instruction trap (since SPP, SPIE, and SIE bits in MSTATUS are not implemented). Therefore, any software which uses SRET will need to be recompiled/reassembled to use MRET instead. This is a relatively simple matter: a global search and replace ought to cover it. I just need to remember this detail.

Which means I need to update my assembler to include the new mnemonics too. Bleh. Forgot about that. Good thing for Github issues.