(RPi/BCM2835 - BCM2835-ARM-Peripherals.pdf):
SPI as a possible SDRAM clock source + SPI-one-shots?
If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125MHz. The practical SPI clock will be lower as the I/O pads can not transmit or receive signals at such high speed.
I have no idea what the system-clock will be... Nor, actually, do I know *WHICH* processor is in which RPi... but hmm... Plausible...
All we really need is the clock-source, the SPI data I/O isn't really relevant. OTOH, it *could* maybe be used instead of one-shots... Hmmmmmm....
PWM as a possible SDRAM clock source:
Both modes clocked by clk_pwm which is nominally 100MHz, but can be varied by the clock manager.
So, yahknow, if it could be bumped up to 200MHz, then set RNG1 to 2, with a *value* of 1... that'd give 100MHz 50%-duty-cycle output (but, again, maybe limited to the pins' speeds).
This datasheet doesn't discuss the source of clk_pwm, nor how the clock-manager affects it.
GPIO output of General Purpose Clock:
The General Purpose clocks can be output to GPIO pins.
The maximum operating frequency of the General Purpose clocks is ~125MHz at 1.2V but this will be reduced if the GPIO pins are heavily loaded or have a capacitive load.
(confusing, aren't the GPIOs 3.3V? Maybe they're referring to the core-voltage?)
(Note, disable the MASH filter)