Ordered parts... settled on the NON-bus-hold devices, but got a couple with bus-hold for testing-purposes. The non-bus-hold devices were available in SOIC, but nearly twice the price... But, since we're in the prototyping phase, decided it was worth the extra couple bucks.

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Also, the prototype has been running quite stably at 30MHz with a 74AHC574 D-latch (for the one-shot circuits), and a couple 74HC00 NANDs for various purposes.

Found an HC574 in my collection, so thought I'd see what'd happen with only these older parts...

Whelp, it doesn't like 30MHz, and 20MHz requires switching the clock input... On the AHC setup, the clock-input goes through a NAND-based inverter. On the HC setup, the inverter needs to be bypassed, and the clock needs to be slower. But, it sorta seems to work, and surely would if I really fought with it.

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There's a bit of hand-waving, here, but basically don't forget that the inverter itself is adding quite a bit of delay, as well. It's not *immediate* with the input-clock. So, realistically, *where* in a clock-cycle the data's being latched is completely up in the air. Then, of course, the HC is significantly slower than the AHC, so even wherever it's actually being latched, the data-output is probably delayed even further.

But, since everything on the SDRAM (address/command/etc.) is synchronized on its rising-clock-edge, and since the SDRAM is pretty fast (propagation-delays, etc.), it shouldn't really matter too much whether things are delayed until the next clock-cycle due to slow parts... That's my theory, I haven't really analyzed it too thoroughly. Mostly just "inverted doesn't work, try non-inverted. Nice."

(Odd... it alleges to be running at 38909 rows per second, but there are 1024 cols/row and the clock is 20MHz... that math doesn't add up. It *does* detect the dimensions of the DIMM's chips, correctly... so... eah... This isn't a huge focal-point at this stage in the game... definitely looks like it *would* work, with a little bit of troubleshooting.)

Though, I'll probably need to analyze this clock-edge stuff a bit more thoroughly when running at high-speed, and also when considering running at *various* speeds.

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But, really, I just cleaned off my desk and set this up so I could finally get to wiring-up the *sampling* stuff... the trigger-handler, circular pre-buffer, etc. There's very little chance I'm going to do all 32 bits in this solderless-breadboarded prototype... I might do one full byte and one bit each from the remaining three bytes, just to make sure it works. But that'll have to wait until the parts come, and I might rather solder this thing up on regular-ol' breadboard, at that point.