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D-FF without metastability

A project log for Clockwork germanium

A retro version of Yet Another (Discrete) Clock, with vintage parts

Yann Guidon / YGDESYann Guidon / YGDES 02/08/2020 at 16:490 Comments

Exploring the First principles of Flip-Flops was very interesting but going back to the basic/classic "Eccles & Jordan" configuration (with 2× PNP or NPN) proved the weakness of the approach. The previous log I don't know why it works shows that metastability creates countless problems : it is very sensitive to initial conditions, operating conditions and parts values tolerances. I don't want to make a circuit that requires fine tuning and works only at a given frequency !

Metastability is when both transistors in the pair conduct. This is a third state of the flip-flop and under certain precise conditions, I would get a flip-flap-flop circuit, for who knows what reason. I tried my best to avoid the metastability but it's a systemic, fundamental flaw of this circuit and even adding parts, or using Ge transistors, the problem still lurks somewhere.

So I went back to some ideas from the earliest log From MUX to Latch and took a second look at the "SCR" approach. And this time I did it right :-)

The basic SCR-latch has 4 resistors and 2 transistors. The only drawback is the complementary configuration : one PNP and one NPN... OTOH it doesn't suffer from the metastability plague and always powers up/initialises properly in "off" state !

The power draw is easy to control, by changing the resistors. I have put "no-brainer" values, with 1K the basic for medium currents. By default I choose 3V for the power supply, because I want to power it with a pair of AA batteries. A higher value has been used for the base NPN's pull-up so it is more sensitive to setting but it is not critical. The values will be adjusted for each application, with an appropriate compromise between speed and power consumption. Slower circuits will use higher resistors.

This circuits is reminiscent of the one discussed at 17. Another interesting BJT DFF circuit so I wanted to try the single-BJT circuit for transferring information from the last stage. Previously I used a different system, where I power the flip-flop selectively but I fear this wouldn't work at high enough speeds. However, a transistor can also be used in controlled ways as an almost bidirectional pass gate !

It is also reminiscent of the TTL gates input circuits, with the added trick that it is controlled by a signal, and not permanently pulled up by a resistor. And swapping the emitter and collector doesn't seem to make any difference.

In fact the BJT can be seen as a pair of diodes so the current from the base can go to the collector and/or the emitter (with more or less chance) IF the base is at a high enough potential. With some luck there is even some amplification :-)

Here the goal is to pull or push current through the base of the slave FF. The direction will depend on the potential of the "source" of current (the master). I found that I had to put a diode to prevent the slave from controlling the master FF...

Here is the link :-)

The latch is really transparent when the clock pulse is high so this is easily transformed into a DFF by adding the pass gate at the input of the M/s pair.

(full source in the description of the video)

Now is the time to turn it into a clock divider...


This circuit should it :

But I'm looking for a trick to perform the inversion, without the extra NPN...

Anyway, it's already good enough for a simple shift register :-)


In the last video, I saw that the 3.9K pull-up was not required. But that was not the end of it ! I'm now trying to design another system with 3 PNP and 3 NPN  though it's very tricky but the potential savings are significant.
Now I wonder where/how I can find enough NPN in germanium...

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