I've been pretty confused by the 2-transistors latch that is shown on the project details page. I've been looking of a simpler, yet compact DFF circuit that uses few transistors.
Today I've done some research on the subject of #CBJT Logic and I came across this PDF : http://orbit.dtu.dk/fedora/objects/orbit:91667/datastreams/file_0b85d918-7d44-40c2-b7c7-a4332b0ce2b6/content
"Figure 5 shows the realization of a triggered bistable circuit with complementary transistors. The set-reset function is here performed by a symmetrical transistor;
if A is 0 volts (true value, "1"), the symmetrical transistor will work as an emitter follower and, by a pulse at its base, set the bistable circuit;
if A is not 0 volts (false value, "0"), the transistor will work as a collector follower and, by a pulse at its base, reset the circuit."
The latching cell contains a OC47 and OC141.
OC141 is NPN germanium, OC47 is PNP (like the OC70 I have).
I am confused by the transistor symbols but I can try to reverse-engineer the circuit...
The right side is the latching part so the base loops to the collector of the other... How do I interpret the OC141 with 4 pins ? Well the right and left are probably the same node...
Creating a latch cell is pretty easy and does not depend on the polarity of the transistor so that's not critical.
What I'm after is a way to change/force the value with the least parts possible and the OC141 on the left does just that. This is the most interesting part !
Let's notice the two capacitors (of identical values: 4.7nF) and the resistor divider (10K, 10K) on the A input.
The capacitor on A stores the data's charge, while the series input resistor isolates it from the source circuit (probably to reduce data leakage while it changes from a simultaneous clock pulse).
The base is clearly (from the text) connected to the resistor divider 22K/2K, energised by the clock signal, through the series capacitor.
The point is clearly how they use a NPN to work as a "pass gate", while the input value is held in the capacitor. The clock capacitor has a similar value so both discharges are simultaneous.
Now, the awaken @esot.eric will notice that when A is low, B is high and a rising pulse appears on T, then the pass transistor is ... reverse biased ? Current will flow from B to the input capacitor (but not A because of the resistor).
Does that remind any Eric of a "almost functioning" circuit with a mistaken transistor ?
Whatever the case, it's very interesting because each DFF uses only 3 transistors, no diode (though I'll add one for the reset), and the circuit can be tuned for other voltage rails. It shouldn't be hard to modify it for an all-OC70 design.
With "only" 3 transistors, plus 2 to drive the outputs, the whole clock system requires something like 39DFF×5=195 transistors. Add some more for housekeeping (oscillator, buffers, drivers, decoders...) and this might reach 250 transistors, which is a desired outcome. The "pass trick" exposed above might be the detail that makes this whole project realistic.