How will the fast speed be accomplished ?

Relays are slow, and to get acceptable performance, many measures must be taken.



The design is shown in the following block diagram (click on it for a larger version):

The block diagram also shows which functions the twelve PCB's and the backplane contain.

Now that all schematics and also all pcb's are designed, I can give a quite accurate listing of the number of main components:


There is an online browser-based Assembler and Simulator that simulates the calculator application (or any other application that you could make). Just press "Assemble" and then "RUN", and start making calculations on the calculator keyboard that is on the screen. (After each button click, have some patience until the script halts and the number (hopefully) appears.) The calculator program does not give messages yet for overflow, or out-of-range input (including zero divide). Trigonometric functions don't work yet, all others do.


The architecture is explained in the architecture document (see Files section). Highlights are:

The architecture is independent from the technology, so it could also be used for a TTL or FPGA design. It can be upgraded to a full 32-bit design. Actually, since there are 32-bit register pairs, it would be easy to support a 32-bit address bus.

Use of the architecture is free for non-commercial use :), but I would like to get a mail when you are going to use it.


What has to be done: