I have been working on this over the years, but now it looks like it is close to be nice useable product - starting from 2015.4 release Xilinx as last FPGA company included their JTAG based debug IP Cores for free in free versions of the tools, this opens new horizons and allows the LabX to be implemented in pretty much known FPGA's. Ok for starters Xilinx...

Milestone 1:

LabX basic support for all 7 and 8 Series FPGA's: Artix, Kintex, Virtex, Ultrasale, Ultrasale+, Zynq, Zynq Ultrascale+ MPSoC.

Milestone 2:

Labx basic board level support for all Xilinx FPGA boards I have access to in our lab.

Milestone 3:

Labx basic board level support for all Xilinx FPGA boards that have full public information.

Status:

Scripts and IPI Design are being setup for Artix and Kintex families.

For TE0725 (Artix A15T, A35T, A100T) board level basic design is ready and openly available.