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A project log for DDL4-CPU

A Modular 4-Bit CPU Design

Dave's Dev LabDave's Dev Lab 06/27/2018 at 18:330 Comments

Many of you from the "software world" will know about using "lookup-tables". This is a pretty common practice when dealing with limited resource or when performance is needed. For the DDL4-CPU decoder, I am using 2 EEPROMs loaded with a lookup table. The original design had a total of 12 inputs, which includes the 4-bit opcode, 6 clock phases along with the Carry-Flag (CF) and Zero-Flag(CF). The CF and ZF inputs were present to handle conditional jumps such as "Jump on Carry" and "Jump when Zero", no other instructions make use of the Carry or Zero Flags. The problem with this implementation is that it increases the lookup-table by a factor of 4. Each input combination needs to be represented in the lookup table even if it doesn't use CF or ZF. An example of this is the command to load immediate data from the ROM to register A (LDA). Four entries in the lookup-table would have to be made. This is some pseudo code that represents the LDA command:

if [LDA==1] ; then 
  if [CF==0 & ZF==0] ; then
        copy data to registerA
    else if [CF==0 & ZF==1] ; then
        copy data to registerA
    else if [CF==1 & ZF==0] ; then
        copy data to registerA
    else if [CF==1 & ZF==1] ; then
     copy data to registerA
    endif
endif

 In this case, there are 4 entries that do exactly the same, no matter what the value of CF and ZF are. Not only does this increase the size of EEPROM needed, but it makes generating the lookup-table a lot more complicated. So, the question then becomes, how to solve this problem and reduce the size and complexity of the lookup-table? Well the obvious answer is to remove the CF and ZF inputs to the lookup-table and deal with the CF and ZF in another way.... to be continued!

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