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R.A.V.E.N. -- A Transistorised Brainfuck Computer

[R]eduction to [A]lgorithms of [V]ersatile [E]soteric m[N]eumonics

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This discrete transistor computer will be based on the DEC R-Series DTL logic, will use hand-made core memory, and will be able to run 'brainfuck' code natively - the full instruction set of this computer will be the eight instructions of 'brainfuck'.

This computer is inspired by the MENTAL-1 (TTL) and BrainfuckPC (Relay) implementations of brainfuck as an Instruction Set Architecture.

This project aims to demonstrate that technological disobedience is possible, and you can have a computer that completely circumvents any proprietary computer corporations!

This project is licenced under the GNU GPL v3.

Please find here a link to my Patreon if you believe my work is important: https://www.patreon.com/dirtycommo

Log #1 - Implementing the Stack, and Defining the Data Flow

Log #2 - Creating the Sub-Circuit Modules in Qucs

Log #3 - First Attempt at Designing the Perboard Layout

Log #4 - Explaining How the RAVEN's Flip-Flops Work

Log #5 - Purchasing the Circuit Board


Technological disobedience is an imperative today. All the biggest CPU manufacturers are all part of the capitalist military industrial complex.

With this discrete transistor computer, I aim to show that it is possible to create a reasonably functional 12-bit computer with a (relatively) low number of parts. If I can complete this project successfully, I will go on to create a design for a discrete transistor computer that more closely resembles the feature set of a proper general-purpose computer.

So this project really is to make something like a toy, but I do want to go on to create a hackable Second Generation computer that allows you to take control of how your everyday appliances are designed, and help you understand how they work, so you can't be fooled or controlled.

--

In order to make the design of this computer as simple as possible, I have decided to follow a popular trend of making a computer with the 8 'brainfuck' esoteric language operations as the ISA of this computer.

That way, an accumulator and an ALU are not necessary for this design. Also, absolutely no general purpose working registers are needed either. All of the operations of the brainfuck esoteric language can be carried out by incrementing and decrementing a Memory Data Register, a Memory Address Register, and including one extra register, a Stack Pointer, in order to speed up the [ and ] commands.

--

This project follows in the footsteps of the famous PDP-8/S, which was the smallest and cheapest commerically available computer when it was released. It was also a masterpiece of engineering, and was not some shoddy gimmick. It combined beautful concepts while still ushering in more democratic access to computing.

This is what I aim to achieve with the RAVEN, of which I only really want to build one model - greater hardware openness and democracy, and education.

I aim to make the RAVEN as cheap as possible to build, so other people can copy my plans and follow along.

I aim to avoid as many of the metaphors and idiosyncracies of the x86, 8080, 8088, and 8085 Intel processors. I think they are ugly and incredibly unparsimonious designs, and I was very dismayed to find that the later Malvino Digital Computer Electronics editions cut out large sections of wonderful exploration in the 70s editions for just copying and pasting explanations of Intel x86 CPU architectures.

I also mean this project to be a big of a 'stuff you' to Microsoft/Windows/Intel. I by far prefer the engineering culture at DEC, and I think the absolute beauty of their computers is evidence that DEC fostered much greater creativity and freedom in their engineering.

(Also DEC had an excellent corporate culture of looking after their employees.)

--

Anyway the take-home message I want to get across is I would love to show people that they can have much greater control and understanding of exactly what their computer is doing, and how it is doing it.

  • 200 × MMBT2907 (AUD3.62) RF, IF, RFID, ZigBee Semiconductors and ICs / Transistors and FETs
  • 300 × 1N4007 (AUD3.19) Discrete Semiconductors / Diodes and Rectifiers
  • 200 × 100pF Capacitor (AUD1.51)
  • 2000 × 1N4148 (AUD13.84) Discrete Semiconductors / Diodes and Rectifiers
  • 200 × 1.5K Resistor 5% 0.25W (AUD1.97)

View all 10 components

  • My Patreon

    Blair Vidakovich08/05/2018 at 17:05 0 comments

    Hello!

    I have ordered all the electronic components necessary to build the flip-flops for the computer. I still have to design a good power supply, however.

    I will post photos of the components when they arrive.

    I will also be conducting live streams of the work sessions I do when I assemble the computer together.

    I have also set up a Patreon account. If you have enough money to spare even $1 per month to help me finish this dream project of mine, I would be incredibly grateful.

    This is the link to my patreon - https://www.patreon.com/dirtycommo

    I have done great research for the homebrew CPU community here on Hackaday. This research includes:

    This essay on DCTL logic: https://hackaday.io/project/8449/log/148234-direct-coupled-transistor-logic
    This essay on DEC R-Series DTL logic: https://hackaday.io/project/8449/log/130460-bizarre-dtl-logic-levels-the-discrete-component-pdp-8

    And this essay on IBM's DTL Logic: https://hackaday.io/project/8449/log/131805-the-electronics-of-ibm-standard-modular-system-logic

  • Circuit Board Purchased

    Blair Vidakovich08/02/2018 at 08:49 0 comments

    I do not have the budget to fabricate fibreglass PCBs, so I must either hand solder veroboard or perfboard.

    Veroboard and perboard is very expensive at good qualities, and cheap board is of terrible quality and structural integrity.


    So, to keep costs down, I turned to re-using waste.

    I am going to use acrylic board (PMMA acrylic) I obtained from the Sydney Marrickville Reverse Garbage centre. It was very cheap, at $18 for approximately 3 metres squared.

    Drilling holes in the plastic will be time consuming, so I will superglue surface mount components to it, and hand solder them once they are attached.

    SMD construction will be more time efficient and will reduce the size of the computer.

    I believe that the plastic can be cut or snapped into ''flip chips''.

    I am open to fabricating ''flip chips'' for others on a not for profit basis.

    The next step is building the power supply and ordering the components.

  • Explaining The R-Series Logic Flip-Flop

    Blair Vidakovich07/27/2018 at 16:01 0 comments

    I received some constructive criticism about the Flip-Flops I am using the construct the various elements of the RAVEN. I think a lot of the apprehension other hackers have about the R201 DEC Flip-Flop I am using is because it contains a great number of circuit elements -- if these circuit elements were in a large part active during Flip-Flop operation, then obviously the R201 would be very slow.

    In this log I'd like to clean up and and explain exactly how the main Flip-Flops in the RAVEN will function. I do not believe these DTL Flip-Flops I have lifted from DEC R-Series Logic are slow, and will result in less than 1 MHz performance.

    The Most Basic Element of R-Series DTL Logic

    The most basic circuit element of any electronic digital logic is the inverter. This is the basic inverter of the DTL logic that the RAVEN uses:

    A couple of examples can be provided which show the actual way this inverter is implemented in R-Series Flip-Chips:

    The R113 Diode Gate

    The R121 NAND Gate


    R-Series digital logic specifies -3V as logical ONE, and 0V/Ground as logical ZERO.

    Inverter Simulation

    Conventional current flows up through the emitter of the transistor, and out through the collector. Depending on whether there is 0V/ZERO or -3V/ONE at the INPUT terminal determines whether current will flow out through the base of the transistor and cause it to saturate.

    -3V/ONE at the INPUT terminal will reverse bias the INPUT terminal diode, and open up a path for current through the transistor base up through the -15V terminal past the steering diodes. The transistor will then conduct, and the voltage at the output terminal will be 0V/ZERO, effecting an inversion.

    0V/ZERO at the input terminal will cause the INPUT terminal diode to become forward biased, making the current path through the transistor base a path of much higher resistance. A small amount of current still leaks through the base through to the -15V terminal near the INPUT, but it is not enough to turn the transistor on. The transistor stops conducting and the voltage at the output terminal is therefore -3V.

    R-Series Logic Flip-Flops

    The simplest Flip-Flop of the RAVEN is two Inverters complementarily connected together like so:

    As you can see, this is the heart of the R201 Flip-Chip:

    What, then, is the rest of the circuitry in this schematic?

    Diode-Capacitor-Diode Gates

    The answer is that the extra circuitry is 'Diode-Capacitor-Diode' gates. This circuit element is a very innovative and useful solution for both (a) edge-triggering; and (b) constructing JK and D Flip-Flops is as little circuitry as possible.

    This is the basic DCD gate:

    The basic principle behind this circuit is that the capacitor charges and remains charged so long as the PULSE INPUT is held at -3V, and the LEVEL INPUT is held at 0V.

    When the LEVEL INPUT equals 0V, and the positive edge of a PULSE INPUT signal changes from -3V to 0V, a positive voltage is generated at the output, which serves as a trigger for a Flip-Flop.

    When LEVEL INPUT = -3V and PULSE INPUT changes from -3V to 0V, no such positive pulse is produced.

    See the following simulation:


    Creating D and JK Flip-Flops

    The process of creating complex, clocked, edge-triggered Flip-Flops is as simple as preparing the inputs to Flip-Flops attached to DCD gates. The following two schematics are isomorphic/identical in meaning:

    A JK Flip-Flop can be constructed by simply sending identical pulse inputs to a DCD-gated Flip-Flop:

    So long as the LEVEL INPUTS are tied to ground, identical PULSE INPUTS will cause a Flip-Flop to complement.

    This simulation demonstrates a JK Flip-Flop constructed from a DCD-gated Flip-Flop:

    This serves as the basis for this Up-Down Binary Counter Register:

    Binary counting is therefore achieved with the minimum...

    Read more »

  • R201 Flip-Flop Perfboard Layout #2

    Blair Vidakovich07/23/2018 at 09:21 0 comments

    This is half the Flip-Flop completed. It is the entire right side of the R201 specification. It now includes that actual Flip-Flop, and the 3 edge-triggered inputs on the right hand side of the design, including the voltage divider.

    This layout corresponds to this fraction of the R201 schematic:

  • Designing The Perfboard Layout #1

    Blair Vidakovich07/23/2018 at 08:05 0 comments

    I do not have the budget to get printed circuit boards made, so I am using some software called Fritzing (link) to do the layout of the components on perfboard.

    This is the heart of the R201 Flip-Flop completed:

    This layout corresponds to the following section of the R201 schematic:

    It is by far cheaper for me to solder a great many of these perboards by hand, instead of etching or paying for the manufacture of PCBs.

    I will hopefully have another update tonight.

  • Creating Virtual Schematics Using Qucs

    Blair Vidakovich07/22/2018 at 03:32 0 comments

    I will be using the Free Software program Qucs to plan out the electronics of the RAVEN.

    The digital electronics of this computer will be based on the R-Series logic of the DEC PDP-8/S.

    I started planning out the registers of the RAVEN, following this 'cookbook' suggestion inside the 1967 DEC Logic Handbook:

    The DIRECT SET lines will not be tied together, and they will not be unbuffered. The DIRECT SET lines will have a three state input implemented with an extra R-Series Diode-Capacitor-Diode Gate attached to each separated DIRECT SET line:

    So the extra 'CLEAR MDR' control signal will be implemented by attaching all DIRECT CLEAR lines together. This will be useful for the CLEAR STACK CELL control signal/sequence.

    Flip-Flops Required for Registers

    This is a 5-input single Flip-Flop as specified by DEC Flip-Chip code R201:

    And this is the corresponding circuit schematic in Qucs:

    And this is the sub-circuit schematic that is generated by attaching ports to the appropriate inputs and outputs:

    Now the registers can be designed (and hopefully simulated) in Qucs and an accurate Bill of Materials can be generated.

  • Log #1 - Designing the Data Flow

    Blair Vidakovich07/22/2018 at 03:13 0 comments

      This is the first attempt at a data flow diagram of the RAVEN. I spent a lot of time researching and analysing the MENTAL-1 computer built by Trey Keown here on Hackaday.io. That computer was built with TTL logic. It implemented a simple but slow 'SCAN' control signal which decremented the Program Counter to a corresponding [ instruction after executing a ] instruction.

      After reading the discussion that Trey conducted on reddit, and seeing that he suggested implementing a stack pointer register in order to speed up the [ and ] looping process in brainfuck code, I decided to come up with a CPU architecture based on the PDP-8/S and Malvino SAP-2 that implemented a stack pointer.

      This is the rough idea I have for the CPU architecture data flow for the RAVEN, after looking at the PDP-8/S and SAP-2:



      The CPU does not require an accumulator, or temporary buffer registers, because the only data manipulation that the brainfuck instruction set implements is incrementing and decrementing memory cells ("memory locations", "memory words").

      So in order to implement the instructions +, -, and < and >, all that is required is control signals from the control sequencer that increment and decrement the MAR and MDR.

      The MAR

      The MAR is not a bidirectional/three state register. After it receives a memory location from the PC, or is cleared to $0000, or increments or decrements itself, it always holds the address locations to which it points in the core memory HIGH.

      Currently I do not want to implement ROM memory, I will implement a tape reader like Yann Guidon's optical-based reader. I haven't checked out how the PDP-8 loaded in programs. I envisage loading programs will be a lot like bootstrapping and running something like an Altair 8800.

      The Stack Pointer; [ and ] instructions

      The SP will be able to be initialised anywhere in memory, but from my time with 6502 Assembly, I would recommend somethere like $XXFF. Instead of a [ instruction incrementing a SCAN counter register like in MENTAL-1, [ will:

      1. test to see if the current stack location is non-zero
      2. if non-zero, increment the stack pointer
      3. then push the next Program Counter (PC) state onto the stack (the memory cell after a [ command is the loop counter),
      4. and then continue execution.

      When a ] instruction is executed,

      1. the stack pointer is incremented,
      2. and the PC state after the ] instruction is pushed onto the stack.
      3. Then, the stack pointer is decremented
      4. and the PC state of the loop counter cell is popped off the stack and loaded into the PC.
      5. The MAR is then loaded with the memory cell location,
      6. and the data is loaded into the MDR.
      7. If the cell is data equals zero (I need to implement a flags register linked to the MDR), the stack pointer is incremented
      8. and the state after the ] instruction is popped from the stack and loaded into the PC,
      9. the stack pointer is then decremented to cause the old [ location to be overwritten, and execution continues.
      10. I think it would probably be wise implement a 'stack clear' operation to write $0000 to the old [ location. This would just require loading the MDR with ZERO, and then writing that to the SP memory address.

      BUT

      1. If the loop counter cell is non-zero, the old ] location is written with ZERO,
      2. and the stack pointer decremented and execution continues.

      The organisation of the stack will look like this, as [ and ] are executed:

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Discussions

agp.cooper wrote 07/24/2018 at 04:00 point

That flip-flop has to be the most horrible thing I have ever seen!

For the CPU that you are describing I am guessing that you will need about 100 to 200 of these flip-flops. Not a pleasant thought.

Have a look at Johnny Lovqvist design:

 https://lovqvist.net/8080/homebuilt%208080%20registers.html

It has less components and likely much faster (at least 10 times faster).

---

Don't take what I am saying too seriously, it meant to be a nudge to show that there may be better ways of doing it out there.

AlanX

  Are you sure? yes | no

Blair Vidakovich wrote 07/24/2018 at 05:25 point

it's a 5 input flip flop with edge triggering!

  Are you sure? yes | no

Blair Vidakovich wrote 07/24/2018 at 06:26 point

I will make a post explaining how the Diode-Capacitor-Diode gate works. It allows complex gates to be constructed with minimal circuitry. Most people go for the multiple NAND gate construction, but DCD gates allow edge triggering AND the transformation to a D and JK flip flop.

There is reason to this!

  Are you sure? yes | no

agp.cooper wrote 07/24/2018 at 08:26 point

I will certainly be interested in the diode steering description.

I have built simplified versions of this type of flip-flop but I found them rather slow (<500 kHz).

I have built the six NAND gate D type Latch (i.e. 7474 type) using DTL and they work fine up to a few MHz. These are dege triggered.

You could possibly simplify your circuit by just opting for an edge triggered D-Latch. I have designed low level simple CPUs using just NAND gates, as NAND gates and D-Latches. But I have not built any of them though. I even designed a 74161 using just NAND gates and the six NAND gate D-Latches. So its all you need.

Why did I not build any of the CPUs? The transistor count was in the order of a 800 transistors.

Anyway, don't let me put you off. One day I may decide to drop down and do a transistor CPU project. But not today!

Regards AlanX

  Are you sure? yes | no

Blair Vidakovich wrote 07/24/2018 at 08:42 point

no real diode steering! this is a simple cross connected bistable transistor configuration with 5 special edge triggering inputs. I can explain in my explanation. this uses less semiconductor material than a 6 NAND edge triggered flip flop. also, i have never been able to construct a clear/presettable DTL NAND flip flop.

ALSO using +10v / -15V rails helps deal with transistor base capacitance.

this flip flop allows: up/down counting, AND buffered inputs. the DCD gate allows edge triggering and buffering in 4/5 diodes and a capacitor.

it looks hairy, but the diodes are just there for buffered edge triggered inputs

from what i can see, lovquist has opted for a master-slave level-based logic, which is simpler, but can introduce race conditions

  Are you sure? yes | no

agp.cooper wrote 07/24/2018 at 14:30 point

Okay, I will have to model it and see how it works.

Not aware of a race condition for the 6 NAND D-Latch but I am not an expert.

The main fault with the Lovqvist configuration is the low noise immunity (~0.3v), but hey it sure does have less components to solder.

Anyway, look forward to your next log.

Regards AlanX

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Yann Guidon / YGDES wrote 07/23/2018 at 20:55 point

It's gonna be mind-boggling...

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Blair Vidakovich wrote 07/23/2018 at 23:54 point

hahaha why??

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Dr. Cockroach wrote 07/22/2018 at 07:17 point

Wow, This goes a lot deeper than my IO BF project. I am really interested in keeping an eye on your core mem progress :-D

  Are you sure? yes | no

Blair Vidakovich wrote 07/22/2018 at 12:59 point

Thanks dude! You're an amazing engineer!

Here's my email! Send me one sometime!

vidak@riseup.net!

Catch you, dude!

  Are you sure? yes | no

Dr. Cockroach wrote 07/22/2018 at 17:23 point

Hey Blair, Thanks back but you are more an engineer than I. I just build and learn as I go and never messed with logic circuits until two years ago :-)

I'll shoot you an email soon :-)

wa4jat@yahoo.com

  Are you sure? yes | no

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