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ALU refining pt 2; updated approach to CPU design

A project log for ECM-16/TTL homebrew computer

16 bit Computer made from ttl logic chips

PavelPavel 02/15/2021 at 09:060 Comments

Following are descriptions of design changes:

1. Some reshuffling of ALU schematic -- mainly for more clarity (compare to schematic in one of the early logs):

Most of the glue logic (individual gates controlling such things as carry flipping at subtraction) were moved to the functional blocks. The blocks themselves are redone with 74 family chip outlines to serve as the reference while building hardware -- as there were some unused pins/gates on those chips, the were repurposed for those glue logic functions.

Operation description:

There are 2 main 16-bit input busses (Src1 and Src2), one 8-bit input (Const), and one 16-bit output bus.

For some operations the 8-bit constant is switched in instead of "Src2", using the Incrementor block;

Next, the signal from "Src2" | "Const" goes through Negator block, which inverts it, alongside with "Carry_in" to facilitate subtraction.

The signals then go in parallel through 4 blocks which do different operations:

- adder takes "Src1" and (+/-)"Src2"|"Const", and outputs 16-bit sum;

- logic operations unit uses the same values as adder, and outputs results of its own operations;

- shifter works on "Src1" input and does simple and arithmetic left/right shifts and rotations through carry;

- barrel rotator also works on "Src1" input, and does rotation to the left (0 to 15 bits)

2. Slight change to command encoding - mending a couple of irregularities:

Previously, there were two ways of doing ALU functions: the one where one of the two source registers was also a destination, and the other where destination could be the third specified register. Now the first version is only used with constant value, otherwise three arguments are specified in the instruction (two sources and destination for two-operand operations).

There also was compare command which was interfering with three argument ops, where the registers 0 and 1 couldn't be used as destination. This interference is now overcome with different encoding of the compare instruction.

3. More top-down approach for overall CPU design:

When starting designing the CPU, I had no clear idea of what the addressing scheme would be, and how all its workings will be organised. The clearest ideas were that this should be 16-bit machine (16-bit data bus, and 16-bit instructions). That was dictated primarily by my assessment of possible complexities: 8-bit will have too complex addressing scheme and instruction encoding -- it most likely would be microcoded. On the other hand, 32-bit would be too much in terms of the sheer number of components needed at the level I wanted to build it (simplest logic gates). So the 16-bit seemed "the golden middle". 

I wanted the machine to have a register file, a number of identical registers which are addressed in instruction, and to have an ALU capable of a adding, subtracting, logical operations and shifts, and also to have an ability to increment/decrement a value by a set number, thus a set of commands with 8-bit constant values. Overall this was constraining me to 8 registers in register file. This is also convenient, as for addressing 8 values, only one 3to8 decoder is needed, which a single IC.

So, the ALU and Register File were the first parts which I had fairly good idea of what I want them to be. Not the other parts. So I started with building the ALU and then Register file in simulator, and then I was adding all other parts in the order I found them necessary at the time. This led to quite a complicated mess, which incrementally grew in its ability and complexity... and in difficulty of understanding of how it all works.

That is why I am restarting almost from scratch (well, many parts are already done, they just need some tidying up), and having more holistic understanding of how I want this CPU to work I will recreate the simulation in a more clear and understandable way.

Following is the high-level scheme of CPU parts:

The scheme summarises the overall CPU design in just 4 main blocks. On a high level it is similar to what I've done up to date, just in a clearer way. The differences are in particulars, mostly in addressing block -- there the 24-bit adder is now present, and 4th 24-bit register is added (Frame Pointer). The presence of adder removes the need to make PC and SP from presettable counters, thus making design more regular.

The blocks:

- Main data path: 

--- eight 16-bit general purpose registers in register file 

--- main ALU (16-bit)

- Addressing

--- four 24-bit memory pointer registers ( PC, BP, SP, FP ) 

--- its own dedicated secondary/address ALU (24-bit)

- Control 

--- Instruction Register 

--- instruction decode circuitry

- Memory ( + memory-mapped input/output )

- Miscellaneous small bits:

--- four 8-bit special registers, (SR, Hi8, OP, IP), placed around the CPU.

--- Boot loading and DMA circuits.

--- Interrupt handling circuitry

--- Some other things I do not know I need yet.

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