A new scope

A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

Yann Guidon / YGDESYann Guidon / YGDES 09/01/2020 at 03:150 Comments

This project will soon go in "shelved mode".

Its scope has grown, extended and now goes beyond the PA3 family : I'd like to add the sxlib or the wsclib, among others, and even those included in the Google-funded Skywater PDK (who knows if I can one day get it).

The PA3-specific code is in fact quite localised and I have found a name for the project : LibreGates ! Look, I even got the domain name that redirects the proper page.

Having a distinct and evocative name helps a lot on many aspects. I struggled to identify or even talk about this project, as you can guess from this project's evasive name. I can now separate the PA3-related code from the gates architecture and the analysis framework, which is now available for any other gates family.

The transition will take a while and the last v2.9 is quite a nice package, but the directories and scripts will be quite different for the new system, far beyond what I considered for v2.10 !

Of course, #Libre Gates will keep the compatibility with the standard proasic3 library. Directory paths are different though but it's not a crazy deal.