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A project log for VHDL library of ProASIC3 gates

Hard macros and "tiles" of Actel/Microsemi's ProASIC3 so I can design compatible and optimised code without the proprietary libraries

Yann Guidon / YGDESYann Guidon / YGDES 08/19/2019 at 20:120 Comments

While reviewing and re-checking the gates versus the handbook, I finally spotted that I made a mistake with xo6 which is in fact axo6. This is fixed in the next release, along with a couple of missing gates. The latches are not included yet though.

I try to focus on packaging, integration and testing, though the perspective of v3 is alluring and I try to clear the path towards this even better system.

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