Close

More gates !

A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 01/04/2019 at 01:390 Comments

I'm adding MAJ3AXO1 as well as some AX1x gates. The definition of the guide is not consistent with the naming so beware ! AX1 should be (A and B) xor C but the manual says it is AX1C. This should be checked with the actual tools so until then, put warnings everywhere...

Give me some time to update, check and upload the new archive...


I just confirmed that the manual definition matches with the generated bitstream. I dumped the EDIF of some test code and collected the following equations :
AX1E  "!((A & B) ^ C)"
AX1D  "!((!A & !B) ^ C)"
AX1C  "(A & B) ^ C"
AX1B  "(!A & !B) ^ C"
AX1A  "!((!A & B) ^ C)"
AX1   "(!A & B) ^ C"

So I must update the INC8 code...

Discussions