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A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 05/11/2019 at 20:020 Comments
https://ohwr.org/project/microsemi-lib

It seems the CERN people are exploiting and even expanding the library. We need to agree on a few conventions to keep all our projects compatible.

A new feature appeared, where errors are injected in flip-flops to test high-reliability redundant designs, using the VHPI interface and external C code. I don't think I'll use this feature because I'm not concerned by rad-hard designs :-)

The gates library might be extended to other FPGA families though it is out of my own scope.

On the one hand, I'm losing some control over the development of the library. On the other, everybody benefits from this consolidation and expansion, where more features are added and cross-tested, and I already have the features I needed initially. The rest is just a bonus ;-)

So that's further proof that, when done correctly, Free Software and Open Source are amazing :-)

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