Yann Guidon / YGDESI added the code to generate all the 15 DFN1* gates.
lt needs some more polishing and some gates are still missing but it's just a few days of work...
I'm already wondering how I will implement the alteration of the DFFs.
v2 with sequential gates
A project log for VHDL library for gate-level verification
Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries
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