Building Blocks 2: Multiplexors and Flip-Flops

A project log for The Spikeputor

I am building a computer featuring a 16-bit RISC CPU made of discrete transistors for learning, fun and art. It will be pretty large.

spudfishScottspudfishScott 12/28/2018 at 16:359 Comments

From simple transistor-based logic gates, we turn our attention to the higher complexity components that make up the essential building blocks of the CPU: multiplexors, to set up the appropriate logic pathway for each instruction, and flip-flops, which become the basis of all of the registers. For this project, the overarching design principal for designing these components is transistor efficiency: We need robust, reliable components made with the fewest transistors. Since, with a 16-bit CPU architecture, each component is effectively copied 16 times for each implementation, even a design with one fewer transistor can make a big difference in the total number of transistors. It also provides increased flexibility for laying out the actual components on the breadboards. After a fair amount of research and building test circuits, the two-input multiplexor circuit shown below was chosen. Instead of the "classic" design with three NAND gates and an inverter (seven transistors), it uses single MOSFETs as a poor-man's tri-state buffer. This works quite well as long as the input signals are buffered, inverting them on input and once again on output, for a total of six transistors. This design can be easily extended to a four-input multiplexor (15 transistors vs. 17 using NAND gates).

For the flip-flops, Wikipedia (borrowing from the TI 7474 chip) provided a nice transistor-sparing design for a positive-edge triggered D Flip-Flop for all the registers:

I was also able to use an XOR gate design that required only five transistors, which considerably simplified the layout (and transistor count) of the ALU's adder function:

Finally, here's a five transistor design for one bit of static RAM that will be used for general purpose output, bank selection, and "screen memory" storage:

Armed with these basic components, it was time to start figuring out how it would all go together to make the Spikeputor CPU.


Yann Guidon / YGDES wrote 01/09/2019 at 03:23 point

Do you mind if I add your own XOR to my XOR zoo ?
( )
I don't yet have a 5-FET gate :-D

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spudfishScott wrote 01/09/2019 at 04:02 point


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Yann Guidon / YGDES wrote 01/03/2019 at 22:02 point

Remember the 2N7000 has a "body diode" so your "pass gate" must be implemented with 2×2N7000 with opposite polarities in series (Common gate and common drain, the in and out are the sources). I'm sure there is a better way to implement a MUX2 than your schematic :-)

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spudfishScott wrote 01/05/2019 at 19:20 point

I had tried to use that two-transistor pass gate very early on when designing the project (I even see it in my notebook), but was dissuaded for some reason. I think it might be because the HI output was just 3.6 volts. Months into the project, I now realize that should be fine, so I'll likely revisit this for the parts of the Spikeputor that I haven't already built. The MUX2 would just be five transistors (four per bit plus one additional to invert S if it's constant for each bit), and the register design would also benefit. Thanks for bringing this to my attention. Always useful to review your design choices every now and then.

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Yann Guidon / YGDES wrote 01/05/2019 at 22:24 point

I agree : we all benefit from nit-picking ;-)

I have a few reels of 2N7002 (or equiv.) for that kind of endeavour, one day...

I have studied CMOS ASIC design (among others) and this provided useful lessons and design tricks.

Usually, when designing MUXes, you have to select/multiplex several signals at once so you can share the inverters/buffers and save some transistors.

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Martin wrote 12/07/2021 at 18:14 point

Yann, why would you connect the drains in common and not the sources? I guess it's about capacitances gate-source and gate-drain?

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Yann Guidon / YGDES wrote 01/03/2019 at 21:40 point

Here are some more XOR topologies for your computering pleasure :-)

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roelh wrote 12/30/2018 at 20:01 point

Scott, did you consider to build the registers from latches instead of flipflops ? This would of course require that the input of a register is never directly dependent from its own outputs, or the output of the ALU could contain an 'isolation latch' to make it possible to send register output to the ALU, do an operation and write back to the same register.

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spudfishScott wrote 12/30/2018 at 21:07 point

That would have definitely been more transistor-sparing for the registers, but would have (as you mention) significantly impacted the overall design (and not sure if the resulting Control Logic would have been significantly more complex). When I started this project, I was pretty much out to copy the design of the “Beta” processor from the MITx course, so it didn’t even occur to me to use latches and one or two strategically placed  “isolation latches” instead of seven full flip-flops. I do like the “toll gate” function of the flip-flop, though it would have been fun to compare and contrast the two designs. Oh well! Maybe for Spikeputor Mark II. As it is, I’ve already completed the full ALU and 75% of the registers as described. Too bad I came to hackaday so late in the game. I’m trying to catch up to real time so suggestions like these can actually be pondered before implantation. In the meantime, thanks for the suggestion. 

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