Memory Pages in Lion

A project log for Lion FPGA CPU/Computer

A 16-bit FPGA CPU I call Lion CPU and a computer, the Lion computer. Everything built from scratch.

LeonLeon 06/28/2019 at 13:530 Comments

When I first started to design the cpu I thought that 16bit address bus is ok for a homebrew cpu but after I made the Lion computer 64K rom+ram seemed very small although it used separate video and sprites ram. I wanted more memory and the more convenient way to do it is using pages. So I added 3 more address pins to lion cpu and added the necessary commands to support 8x64K pages.

The SR register was extended from 8 to 16 bits and now the 9 most significant bits bit15 to bit7 hold the current code (bit15-bit13), data (bit12-bit10) and stack page (bit9-bit7).

Instruction SDP sets the current data page, SSP sets the current stack page

PJMP jumps to another address/code page.  PJSR jumps to a subroutine to another address/page and PRET returns.

Also another register named OtherDataPage ODP assists in data transfers between pages by holding a source or target page for use with instructions PMOV PMOV.B

Interrupt routines always use page 0 as a code page.

I'm currently testing the functionality of this implementation and need to make more changes to the assembler