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Stage 4, Adding 16-meg DRAM

A project log for Building a 68030 computer in 5 stages

Based on Tiny030 design

PlasmodePlasmode 03/02/2019 at 13:290 Comments

Stage 4 hardware construction is manual intensive.  Installing U6-U8 (74HCT240) and socket for 16meg SIMM72 memory are straightforward, but there are many DRAM-related connections that are not hooked up in pc board.  Here is a list of connections that need to be manually wired:

SignalCPLD pin68030 pin
A2134A8
A2235B7
A2336A7
A2437A6
A2539B6
SignalCPLD pinSIMM72 pin
nRAS7644
nCAS08140
nCAS18043
nCAS27941
nCAS37742
nSIMMWE7347
SignalCPLD pinU7 (74HCT240) pin
nENCASA751
nENRASA7419
SignalU7 (74HCT240) pinU7 (74HCT240) pin
floating
Input
8Ground (10)
floating
input
17Ground (10)

The CPLD equations will need the DRAM controller and refresh logic added.  The refresh is CAS-before-RAS driven by a timer and logic that delays the assertion of 68030 DSACKx signals until CAS-before-RAS refresh cycle is completed.  This hidden refresh operation occurs once every 128 clock invisible to the 68030.  The DRAM controller is a digital delay tap clocked on rising as well as falling edge of clock.  Two wait states are needed to access the DRAM.  The design can be improved by using 74157 mulitiplexer to reduce the wait state to 1. 

The 16-meg DRAM memory map is from 0x1000000-0x1FFFFFF.

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