Development on the V9958 board continues apace, and after a false start due to a silly mistake in the first revision things are back on-track with a revision 1 prototype. The design is now validated and working really well. So far it's baby-steps in terms of software, with just enough to show an image.
That's the board image from the website, scaled to a suitable size for the V9958 and reduced to 256 colours. It's bundled in with the code that sets up the VDP and copies the data into video RAM (64KB populated in this image, just enough for testing). Output is RGB via SCART, using a six-pin DIN connector which is compatible with readily-available cables designed for BBC Micro and Acorn computers :)
(Aside: There's also a header on-board with RGB and sync signals that will be compatible with things like http://www.jrok.com/hardware/RGB.html for those in non-SCART countries, and I plan to do a small daughterboard based on some CXA1645s I have lying around that will fit that header too).
Address decoding and selects for the VDP are handled by a couple of 16V8s, and the decoding is specific to the address range needed by the four ports the VDP exposes. I was keen not to repeat the short-sighted mistakes made earlier (with the MC68901 for example, which greedily takes all of odd IO space), and going forward will be doing the same with all the expansions. The next main board revision will also fix the underlying issue with the MFP decoding too.
Programming the V9958 is actually quite a nice experience. I've not done any real "in-anger" work with it yet, but what I have done has been pleasant. Its register set-up isn't especially arduous, and it has some nice features like auto-increment for both VRAM address and register number that make things nice and manageable. The documentation is pretty great too, though it's a bit unfortunate that one has to consult the original 9938 documentation in conjunction with the changes listed for the 9958 in a separate document. I suppose when these documents were current they would have been actually printed on real-life paper, so it makes sense that there wasn't a completely new document for the (relatively few) changes between the 9938 and the 9958.
I did run into a slightly odd issue that took a little bit of debugging (here, MAME once again proved worth it's weight in gold) - it turns out that the V9958 is a little bit picky about the order of things during initialisation, and this isn't totally obvious from the manual. Being able to single-step things and view memory in MAME was invaluable.
In the end, the code to display the image above is quite compact. This is the meat of it, including complete set-up of the VDP, switching to G7 mode, and copying the data to video RAM (the 'SLOWDOWN' subroutine referenced below is simply three NOPs and an RTS):
; Set mode G7, disable interrupts and enable output move.b #%00001110,PORT_WREG_SETUP ; Write DG=0,IE2=0,IE1=0,M5=1,M4=1,M3=1 move.b #$80,PORT_WREG_SETUP ; To register 0 move.b #%01000000,PORT_WREG_SETUP ; Write BL=1,IE0=0,M1=0,M2=0,SI=0,MAG=0 move.b #$81,PORT_WREG_SETUP ; To register 1 ; Set PAL mode move.b #%10000010,PORT_WREG_SETUP ; Set 212-line, PAL mode... move.b #$89,PORT_WREG_SETUP ; .. to register 9 move.b #%00000000,PORT_WREG_SETUP ; Select BG: GGGRRRBB move.b #$87,PORT_WREG_SETUP ; .. In VDP register 7 move.b #%00001010,PORT_WREG_SETUP ; Select 64K DRAM, disable sprites move.b #$88,PORT_WREG_SETUP ; .. In VDP register 8 ; Set pattern layout table to 0x0 move.b #%00011111,PORT_WREG_SETUP ; bit 16 of 0x0, constant 11111 move.b #$82,PORT_WREG_SETUP ; .. to register 2 ; Set up to write VRAM at 0x0 move.b #0,PORT_WREG_SETUP ; VRAM Base at 0 move.b #$8E,PORT_WREG_SETUP ; > register 14 move.b #0,PORT_WREG_SETUP ; Set VRAM A0-A7 move.b #$40,PORT_WREG_SETUP ; Set VRAM A8-A13, and write enable move.l #_image_start,A0 move.l #_image_size,D0 bra.s .COPYSTART .COPYLOOP: move.b (A0)+,PORT_RWDATA bsr.s SLOWDOWN .COPYSTART dbra.w D0,.COPYLOOP move.l #$10000,D0 subi.w #_image_size,D0 bra.s .CLEARSTART .CLEARLOOP: move.b #0,PORT_RWDATA bsr.s SLOWDOWN .CLEARSTART: dbra.w D0,.CLEARLOOP
I'm really looking forward to doing more with this, and can't wait to actually get some redrawing going on in the vertical retrace.
There's a couple of tweaks to make to the board for added buildability and stability, and then it'll go off for manufacturing. I'm hoping to launch it on Tindie in a few weeks time.
In the meantime, as well as video software, I'm also making a start on fixing the slow UART that has been a problem for a while. The 68901 was a great chip to get started with, and still has its uses, but we've outgrown its UART. I have a bunch of MC68681s, and the time has come to use them! More about that in a future log :)