It's Alive.

A project log for FBus: Open FPGA Realtime Bus

Defining and implementing a bus protocol that is built around low-cost FPGAs to enable modular and affordable control and DAQ systems.

flowflow 04/26/2019 at 22:040 Comments

A little bit of verilog

module blinky(CLK50, PW39, NW39);
  input CLK50;
  output PW39;
  output NW39;

  reg [24:0] count;
    always @(posedge CLK50) begin
      count <= count + 1;

  assign PW39 = count[24];
  assign NW39 = count[24:13] < count[12:1];

The SymbiFlow toolchain and a lot of serial interface debugging and the FPGA finnaly shows some life: