I don't have a prototype yet.  My plan is to use a Xilinx Artix FPGA and
a DRAM.  Why not a cheaper FPGA?  Because I want it to eventually
support SD Express (PCIe 3 with 1GB/s of throughput) without consuming
too much power.  The maximum power of a removable SD card is 1.80W (data
from SD simplified spec v6.00, might change in v7.0).  This adapter
should take a fraction of that.

A DRAM stores the grain mapping.  Encryption and decryption of the disk
image is done in hardware.  A soft CPU is also used for things like
initialization and updating image metadata.  I'm currently using the
Microblaze, but I don't mind switching.

Since I don't have a PCB yet, I am testing my code on a Digilent Arty
S7-50.  The connection is straightforward.  My connection is configured
in the file adapter/adapter.srcs/constrs_1/new/sd_host_if.xdc.  You'll
probably want to change it.  sd_host_if_dat, sd_host_if_cmd, and
sd_host_if_clk connect to the corresponding pins of an USB SD card
reader.  sd_host_if_dat3_pullup is connected to CD/DAT3 through a 47KOhm
resistor.

Some of the challenges to me:

I need a name for this project.

I don't have the latest SD full specification.  But the simplified
specification is badly written besides having some parts omitted.  This
problem is partly mitigated with the MMC specification.

I have to figure out how to fit everything in 2.1mm by 32mm by 24mm.  It
includes an FPGA, a DRAM, the voltage regulator, and a micro SD card
socket.

The adapter should present to the host a formatted disk.  We should also
allow it to present to the host a disk of size as big as the space left
on the micro SD card.  That means running mkfs on the adapter.  It is
possible to run Linux on a MicroBlaze.

I need a way to generate random keys.

Parts I have:

The storage format.  Some parts are still to be figured out.  And my
writing may be bad.

A mostly working AXI lite bus SD device interface.  It supports
generating responses in hardware.  But it only supports the SD bus.  We
also need SPI and UHS-II interfaces and possibly NVMe in the future.

The storage format: https://github.com/eywdck2l/cvtm-format

The code: https://github.com/eywdck2l/adapter-parts