CPU BLOCK DIAGRAM
Main parts are:
- 4 data registers D0 - D3 (16 bit)
- 4 address registers A0 - A3 (20 bit)
- 16 bit ALU that can do only ADD, MOV and NOR
- shift unit that can shift one position to the right
- instruction register
- Single memory for program and data
Every instruction needs two cycles:
This will let the ALU calculate a new value and put this in the shift unit. Or it will store a data register in memory.
The inputs for the ALU are:
- a data register and a memory operand, or
- a data register and an address register
For memory operands, the address comes from an address register and displacement, or it is a zero-page address. Immediate operands can be selected by using the program counter as address register (and using a displacement).
The contents of the shift unit is transferred to the destination register. The contents can be either shifted or unshifted. The PC (address register A0) is connected to the memory address. The next instruction is fetched from memory and is put in the instruction register.
Incrementing the PC will be discussed later.
DATA FLOW FOR MAIN INSTRUCTION TYPES
This shows how data from memory is added to a data register.
The ALU can also do a MOV or NOR operation. By making combinations, the following functions can be obtained:
- LOAD: The ALU can transfer the memory data to a register without change.
- CPL: A register can be complemented by NOR'ing it with the value #0.
- SUBTRACT: Complement one of the operands. Then do the ADD and finally ADD #1.
- OR: Do a NOR followed by complement-register
- AND: First complement both operands, then do NOR
The same instructions can be done when the operand comes from an address register instead of from memory. The displacement value (part of instruction word) is not used here. This opens the possibility to use these bits to enable other functions, like shifting or add-with-carry.
Finally, storing a data register is straightforward. There might be separate instructions for store-word and store-byte.
Several topics will be discussed later:
- incrementing the PC
- conditional branches
- carry handling
- loading the upper 4 bits of address registers
I can already uncover a bit more by showing my nice drawing: