New instruction set

A project log for Kobold K2 - RISC TTL Computer

A 16 bit RISC computer with video display, from just a few TTL and memory chips.

roelhroelh 11/03/2019 at 13:570 Comments

Here is the new instruction set. It is quite conventional (thats my personal view), but has a few quirks due to the fact that a lot of functionality was pushed into the instruction set, while keeping the decoding circuits very simple.

I will present the new set in three encoding tables, starting with a few simple ones.


There are two ways to address memory:

All four data registers can be written to memory, either as word or as byte. To write an address register to memory, first move it to a data register and then write it.


Address registers can be incremented with a value from 1 to 31. This can also be conditionally, mostly used in combination with A0 (PC). So the branches can skip 15 instructions at most. For greater distances, 16-bit immediate conditional jumps must be used. Note that the destination of the addition can also be a data register.


This may look a bit complex. But you just pick an instruction, a source and a destination.

Note that there are many ways to specify the source operand:


Remarks for address register destination:

[ edit 20191115: I pushed some more functionality in the ISA, schematic in file section has been updated ]

[ edit 20191119: new schematic uploaded to file section ]