Z80 I/O Emulation - Hardware

A project log for 3-Chip Z80 Design

Combining a Z80 retro design with a modern PSoC CPU. 09/23/2019 at 15:190 Comments

Z80 I/O peripherals can be emulated by the PSoC. The Z80 I/O timing is:

The Z80 address bus is stable 107 nS min (26) prior to IORQ* falling edge which provides the setup time for the address register. PSoC AdrLowIn status register is the Z80 latched address which is read by the PSoC. The register is latched with the falling edge of IORQ*.

The PSoC reads the AdrLowIn status register and determines which peripheral needs to be emulated based on the address. This operation is gated by an interrupt generated when IORQ* and (CPURD* or CPUWR*) are present. This looks like:

The qualified I/O transfer sets the RS Flip-Flop for the interrupt to the PSoC and automatically causes the WAIT* to be asserted to the Z80. This is cleared by a write to the IO_Ctrl_Reg which is configured to generate a pulse when the CLR_IO_INT bit is written.

The PSoC reads the IO_Stat_Reg to determine the operation that the Z80 requests with the IO_Stat_Reg.

Data Mailboxes

There are two 8-bit mailboxes. There is a send mailbox (to Z80 from perspective of the PSoC)  There is also a receive mailbox (from Z80 from the perspective of the PSoC).


Sequence works like this: