Interrupts on the PSoC

A project log for 3-Chip Z80 Design

Combining a Z80 retro design with a modern PSoC CPU. 11/05/2019 at 15:430 Comments

In the last log we added support for interrupts on the PSoC. To summarize:

After Reworking RESET* to the Expansion MCP23017

After doing the rework to the card, it now processes interrupts consistently. The ARM Core no longer gets heap errors, etc. However, the bounce of the switches is now a problem. If the code is set with a breakpoint at the end of the I2CINT_ISR routine it shows all key presses and releases are being received. If the ARM is running full speed it looks like some presses are being missed.

Possible Ways to Debounce and Have Interrupts

One way might be to disable interrupts when the interrupt is received and then use a timer to only enable interrupts again after some number of mSecs have gone by. That has the potential to be relatively simple. Would be the first time I've explicitly used timers, though.