Building a Drop-In Replacement for the MOS6526

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Just out of fun and curiosity, I started in August 2018 to analyze, dissect, study, comprehend, and replicate using 74xx logic ICs the MOS6526, also know as CIA, used by many Commodore computers.

Inspired by the the goal of this project is to build a drop-in replacement for the MOS6526, also know as CIA, used in many home computers by Commodore.

The final design aims to be build out of 5 boards:

  • Board 0: DDR and PORT
  • Board 1: Timer B
  • Board 2: Timer A
  • Board 3: TOD
  • Board 4: SDR and ICR

Board 0 will also include the main computer interface, so it will include a connector to be attached to the computer itself.

There are 3 vertical buses that will extend over the 5 boards carrying different control signals:

  • ENABLEBUS: The 4-bit address selector is decoded into 16 individual enable signals, one for each register
  • DATABUS: The 8-bit data bus from the computer, plus some other neccesary signals
  • CONTROLBUS: Different control signals that are exchanged between registers

  • Once upon a time, there were two little TIMERs...

    Daniel Molina10/12/2019 at 21:30 0 comments

    I've spent quite a few hours this weekend here

    It's starting to look a lot like my bedroom when I was a kid, not sure if that's good or bad though...  :D 

    Using a small piece of assembly that took me 2 hours to complete (I've got so rusty)

    I've been able to try plenty of stuff. There are some things remaining that will need some heavy use of my logic analyzer, as timing's crucial.

    The good news so far :

    • Starting values. Timers' latches should be set to 1, control register to 0. Big facepalm here, as I completely messed up the schematics, a (very much) needed inverter is missing. As a consequence, Timers' latches are perpetually set to 1. Some PCB hacking has been done and, now they initialize with rubbish, but at least I can write to them. An easy fix for rev 2. Control registers initialize OK
    • PB7 and PB6 override. Setting the bit in the control register forces PB6 and PB7 as outputs. 
    • Timer reloading from latches. Works fine, whenever a write to the high byte with timer is stopped, whenever FORCELOAD is written with a 1 (which is stored nowhere), or whenever there's and underflow
    • Timer output on PB6 and 7. TIMERB toggle output works. Pulse output requires the logic analyzer to check. TIMERA output is completely missing. Circuits are the same for both timers, so could be caused by a bad solder
    • Timer B won't count Timer A underflows. Could be related to the above issue
    •  One shot mode. It works, timer counts down until the overflow happens, Then relatches the value.... but then it ticks once more before stopping. Same for both timers. 

    The untested bits:

    • Pulse output. 
    • CNT pulses counting
    • Different overflow behavior counting PHI2 vs CNT (4-3-2-1-4-4-3-2 vs 4-3-2-1-0-4-3-2-1-0)

    And the know issues:

    1. TIMERA underflow seems to fail. Could be a bad solder
    2. START bit gets set to 1 on its own sometimes. Same for both TIMERS. 
    3. Adittional tick in One Shot Mode. I think this is caused by the 2 DFF feeding the clock to the Timer. When Timer stops, there more clocks in the queue. I probably need to clear one of them when the underflow is reached.

    All in all... I'd say it's a 7/10 score so far. START bit has me scratching heavily my head... but I think I should better sleep on it. I've had no ideas about what's causing this so far.


  • Poor old PHI2...

    Daniel Molina10/09/2019 at 20:52 0 comments

    Some quick tests, and I've managed to find the cause of the issues I was facing.

    See, this is a pretty much normal PHI2

    And this is PHI2, when I added the three boards.

    So awful!

    Of course, nothing running on PHI2 worked. Not CIA#1, not CIA#2,  probably not the SID, not even my 'thing'.

    This is caused by PHI2 being fed into too many inputs, up to 18. Old NMOS technology can't pull up fast and hard enough, so the rising slope of PHI2 was slowed too much.

    Adding a single non-inverting buffer to pass PHI2 through has been enough to fix the problem, and now I have all 3 boards working.

    Next task... prepare an intensive test suit for the Timers. There are just toooo many quircks about them!


  • B1+B2 completed. Also, facing my first real problems.

    Daniel Molina10/06/2019 at 14:42 0 comments

    Finally, B1 and B2 are completed and they.... kinda work... Although I'm going to have to check quite a few things.

    Remember how B0 performed flawlessly, both when connected via the expansion port, and when replacing CIA#2? Well, that's no longer true. I'm getting weird image artifacts when doing that, even using only B0. All registers work OK when connected into the expansion port, so it seems something's wrong with the port outputs. Until I figure it out, I'll do only testing via the expansion port.

    Now, about the new boards, I've only been able to do some limited testing. Timers start and stop, and the do count as expected. B0+B1 work, B0+B2 work too. However, if I connect the whole stack (B0+B1+B2) my C64 starts to behave weirdly. I get no cursor and no keyboard. This implies CIA#1 no longer works. I get the startup screen, and Run/Stop+Restore does what it should, so CPU, VIC.. they are pretty much OK. I may be drawing too much power and CIA#1 is the first victim, or some other signal may be being affected.

    Something I didn't take into account is how many inputs can I drive from the C64 outputs, and I'm maybe paying for that now.

    So, plan for the next couple of weeks. Run some extensive testing on both timers individually, identify why B0 seems won't work properly on its own, and find what's going on when I connect the full stack.

    After an uninterrupted successfull streak of 14 months, with no issues at all, this feels weird but... I couldn't be so easy. At least, no C64's had been damaged so far :)


  • Ain't it beautiful?

    Daniel Molina09/29/2019 at 15:18 0 comments

    It's been a busy weekend! But here they are. TIMERA on the left, TIMERB on the right. Each one accompanied by its CREG!

    The four empty spots on the left of each board are for 4 bit counters, to complete the 16 bit counter for each timer. They should be here this next week.

  • B1, B2 and (most of) its components arrived in the mail.

    Daniel Molina09/26/2019 at 14:44 0 comments

    I've cleared my agenda (it wasn't too busy anyway) this weekend to assemble both B1 and B2, which correspond to both TIMERS and CREG. I'm still missing some ICs (mainly, some 4-bit binary counters) that should arrive soon, so I won't be able to carry out too many tests.

    Meanwhile, analisys and design of the remaining units (TOD, SDR and ICR) is around 75% complete. I'm hoping to start working on their schematics by the end of October.

  • B0 is complete.

    Daniel Molina09/23/2019 at 12:13 0 comments

    Board 0,  which includes DDRA, DDRB, PORTA, PORTB, and the 65xx bus interface is completed.

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Dan Maloney wrote 09/25/2019 at 16:20 point

This is pretty cool. Looking forward to seeing the whole 5-board stack in action.

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