Ideas and Influences

A project log for Suite-16

Suite-16 is a 16-bit cpu built entirely from TTL. It is a personal exploration of how hardware and software interact.

monsonitemonsonite 10/17/2019 at 13:200 Comments

Suite-16 has been on the back-burner for a number of years, distilling my thoughts slowly and absorbing the deep aromatic influences of past generation computer hardware.

A Little History

One of my main influences is the PDP-8 which became the first mass-market minicomputer in 1965 - the year I was born. 

With an estimated 50,000+ machines sold over its 10-15 year lifecycle, it was the first of the accessible minicomputers, pre-dating the microprocessor by almost a decade.

It evolved out of the earlier PDP-5 (1963) - a minimal 12-bit design, which very nearly was not a computer at all. With just 8 instructions, 4K words of core memory and a memory cycle time of 6 microseconds, a 12-bit addition took 3 cycles or 18uS to complete.

Despite its limitations, the PDP-5 was the first of the DEC machines to exceed 1000 sales, and it convinced DEC management that there was a market for a small, cheap machine. So the PDP-8, introduced in 1965, evolved out of the PDP-5 with an enhanced instruction set, and a faster memory cycle of 1.5uS. 

The PDP-8 spanned the era of rapid hardware developments, so it was built in several versions - each taking advantage of the latest hardware improvements. The last of the PDP-8 were implemented as an LSI chip (Intersil 6100 and Harris 6120) and were integrated into VT-78 data terminals and DECmate word processors in the late 1970s and early 1980s.

When the PDP-8 was first introduced, core memory and its associated complex driver circuits were expensive - and often accounted for more than half the cost of the system. Nowadays with very cheap and fast semiconductor memory a lot of the complexity and expense can be stripped out from a modern design.

The PDP-8 used a very simple 12-bit instruction word - and instructions (at that time) were expressed as four octal digits. The first octal digit defined the instruction operation, of which there were only 8 instructions.  Two further bits defined the addressing mode - either direct or indirect, and whether the address was the current page or zero page. Finally the last 7 bits was the address of the memory to be referenced.

A 12-bit instruction is very cramped and does not give much room to manoeuvre.  

Suite-16 takes the basic PDP-8 concept, but extends it out to a 16-bit wide instruction.  This means that you can have 16 instruction opcodes rather than 8, you can have a 4-bit field to define the register or the addressing mode - rather than 2 bits, and you can use the last 8 bits to address a 256 word page of memory or an 8-bit literal or index. 

Additionally we are no longer working in Octal, the 4 bit wide bitfields lend themselves to being expressed as 4 Hexadecimal digits.

With 16 opcodes we can divide that into 8 memory access operations and 8 ALU operations.

Memory Instructions

We can code into the memory access instructions a bit that determines if they are a Load or a Store operation and another bit that signals whether direct or indirect addressing mode is to be used.

ALU Instructions

With 8 opcodes dedicated to ALU operations we can have a more capable ALU and have logic instructions such as AND, OR, XOR, INV and dedicated instructions for ADD, SUB, INC and DEC.

Memory Addressing

Much of the flexibility of a particular instruction set comes from the various addressing modes that it can offer.  Each new addressing mode adds further hardware complexity, and so it is often a compromise between flexibility and complexity.

The lower byte of the Instruction word IR7:0 - which is referred to as Payload in the diagram above, is a general purpose 8-bit bitfield that may be used for a variety of purposes. Following the instruction Fetch cycle, the instruction is latched into the instruction register and the Payload is also latched - so that it is available during the execute cycle.

One of the obvious uses of the Payload is to use it as a zero-page address in memory.  The first 256 locations in RAM can be directly addressed using this 8-bit value.

Extending this concept a little further, if we fill in the register field, then one of the general purpose registers can be used to supply a further 16-bits of address - allowing a full 24-bits of addressing capability or 16M words of memory.

Group 0 Instructions

Currently in the Group 0 instructions,  - those where the Opcode is 0, we have conditional branching instructions, Call and Return and  6 unassigned instructions. I had intended that some of these instructions would be able to access I/O and this is still current thinking, but through OPR there exists the possibility to manipulate the accumulator and other hardware directly.

Conditional Branching

First we have to look briefly at how Suite-16 handles conditional branching instructions.

The diagram shows how we incorporate these into the Group 0 instructions. These do not have to address any of the general purpose registers - so the bitfield IR11:8 is available to use for other purposes.

With IR11 set to zero we indicate that the instruction will be a branch. Conveniently we can encode any of the 6 relevant branch conditions into IR10:IR8 including a BRA - Branch Always and a long jump, JMP  which gets its target from the 16-bit word contained in the next instruction.

         00        JMP    16-bit                        Target = @(PC+1)
         01        BGT    AC>0                          Target = IR7:0
         02        BLT    AC<0                          Target = IR7:0
         03        BNE    AC!=0                         Target = IR7:0
         04        BEQ    AC=0                          Target = IR7:0
         05        BGE    AC>=0                         Target = IR7:0
         06        BLT    AC<=0                         Target = IR7:0
         07        BRA    Always                        Target = IR7:0
         08        CALL   16-bit                        Target = @(PC+1)
         09        RET    Return

 CALL and RET instructions also fall into the Group 0 category. More on these later.

OPR Instructions

One of the most useful and powerful features of the PDP-8 instruction set was the use of OPR or "operate" instructions. At the time these were referred to as microcoded instructions - but not in today's use of the word.

The micro-instructions allowed direct control over the hardware, using the individual bits in the instruction to control the hardware. This is a powerful technique - and one that I'd like to incorporate into Suite-16. 

If IR11 is set to 1, this signifies the Call, Return and OPR instructions.