From the Book
The unit "that unifies all of the computer elements" built so far is the Control Panel. It consists of two major parts, a display panel
to tell the operator (you) what program instructions to perform, and a drum memory
device to hold those instructions. The drum memory was by far the most complex of all the components described in the book. It was constructed from a tin can wrapped in paper with holes (much like their decimal to binary encoder), a frame, and many, many paper clips. Here is the construction diagram:
Despite the complexity of the drum memory, the Control Panel implementation in the book is very simple. The Working Digital Computer supports 10 different instructions and the 16 addresses that those instructions can act upon. Here they are:
There is a paperclip "contact" for each individual command and address, plus two contacts for "timing", and another to act as the common ground for all the other contacts. That makes 29 in total. Each command and address contact is connected to an appropriately labeled light on the display panel. The timing contacts drive two lights beside the rotating drum that alternate being on indicating even and odd instruction lines. Like I say pretty simple.
My first thought was that the 29 paperclip contacts seemed pretty extreme. I have a great deal of respect for gort59 for getting this to work in his wonderfully authentic Working Digital Computer build (as seen in the video in the Details section). I understand that he used the small springs from ball point pens which may have helped. Still kudos gort59!
I had also at this point decided to take advantage of my beefed up ALU and add 6 more op codes bringing the total up to 35. Thats a lot of switches leading to a lot of potential points of failure. Given that the total number of commands and addresses were both 16 or less, and that I already had a 4 to 16 decoder designed and working for the Output Panel, I decided to implement a 10 bit encoded instruction instead. This is what I came up with:
Each instruction would have 4 bits for the op code, 4 bits for the address, and I would keep the 2 timing bits as is.
The advantage of having a single bit for each command and address is that an instruction can have more than one "address" bit for each op code. For example the STO command would have an Address C bit to enable the Core Panel (essentially power the panel - this feels more like a control bit to me than an address) and a Core n bit to indicate which word to store the value of the accumulator in. With encoded addresses this is not possible, so some small tweaks to the implementation were required. For the above example I eliminated the Address C address altogether and will enable the Core Panel if any of the Core 1 to Core 5 addresses are used. Here are the other small changes:
- Display ACC removed. Like the Address C bit this would be added to any command that required the accumulator to enable the ALU. Since this is most commands I will simply leave the accumulator "on" all the time.
- JMP changed. The JUP op code used in the book just seemed very wrong to me.
- ENJ command added. The COJ and JMP instructions used the 1-4 addresses as a way to label the target instruction for the jump. They can still be used this way for instructions that do not take an address (like ADD for instance), but for instructions with an address (like STO for instance) an ENJ instruction with the target 1-4 can be added just prior.
- ORA command added. Boolean Or the A and X registers. Store result in A.
- XOR command added. Boolean Exclusive Or the A and X registers. Store result in A.
- AND command added. Boolean And the A and X registers. Store result in A.
- INV command added. Boolean Invert A register. Store result in A.
- NOP command added. No Operation. Do Nothing.
- BCD address added. I'll cover this off in a future log.
With the more compact instruction size I built my drum memory unit:
I guess the design should come as no surprise. It uses the same pegs and switches as the Input Panel and ALU encoders. The right 2 "rings" have alternating pegs to trigger the even/odd instruction lights. One command line is visible, a STO Core 2 instruction.
The one disadvantage of this design is that the peg size doesn't allow for very many instructions lines on this 80 mm diameter cylinder, only 20. The one from the book has 50 program instructions. I have another design in mind for a "high density" drum memory using magnets and reed switches (so predictable).
Finally here is the Control Panel with two 4 to 16 decoders ready to be wired and connected to the instruction memory drum.
The new BCD command has not been added yet either.