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Revision 5 Circuit Design Underway

A project log for VDC-II

Commodore 8568-inspired (and mostly compatible) video core for driving VGA-type displays.

Samuel A. Falvo IISamuel A. Falvo II 10/08/2020 at 18:050 Comments

As I continue to read up on my responsibilities for working with Crowd Supply (CS), I realize that, being a vetted interaction process, CS is almost certainly going to call me out for not exposing all of TinyFPGA BX's I/Os.  So, I'm going to head that issue off now and work to expose all of the I/Os that this module has to offer.  This will in effect turn the card into a generic FPGA development card.  I'll mention more about this in a related but separate project log update.

This is not as simple of a task as it sounds; I need to:

These steps took me about three days so far, and I'm still working to complete the list.  Here's a summary of the changes I've made to the design so far and what can be expected from revision 5A boards.

First, the dedicated 2x7 pin socket that I'd intended to replace the 14-pin DIP socket (in an unreleased revision 4B PCB design; you can see it in the Github repo though) has been replaced by a set of three 2x6 pin sockets, spaced 0.9" apart, and whose pinouts comply with Digilent's Pmod interface specifications at 3.3V.  I'm currently placing them across the top of the PCB for easy access, as that's the only edge long enough to accommodate them.  This brings 24 I/Os out for general purpose use.  There's a catch, though; these sockets are not right-angle sockets.  I intend these sockets to be used with Digilent's 12-conductor Pmod cables to attach devices to.  The PCB is already big enough to flop around in the RC2014's single row backplane socket, so you don't want to put too big of a load on those sockets.  Building a mezzanine card will extend the height of the PCB, which will make it more floppy and less mechanically sound than it already is.  Cables can be routed, which enables them to also act as strain reliefs.  That said, if I can source through-hole, right-angle connectors, they should be drop-in compatible, if you can find a way to mechanically secure the contraption.

Second, I will bring out the 5 shared I/O pins to a 2x3 pin *header*.  This header will have a comparable pin-out to the TinyFPGA BX pin cluster.  Being that these will be exposed pins, you can connect to them using Dupont connectors.

Between these two changes, the BX's remaining 29 I/O pins will be fully and much more easily accessible to hardware hackers.

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