The core of this board design is based on the various reference board designs. The main difference is that the bitbanged I/O pins are not really used except for the 1861 glue (you could use them I guess) and instead the top 256 bytes of memory are used as an I/O window to 'real devices'.
A 74HC573 demultiplexes the rather strange two stage multiplexed address bus and a 74HC688 generates the RC2014 style IORQ and MREQ lines from it. A 74HC14 is used to clean up the reset line which on most RC2014 backplanes doesn't have the needed sharp edge.
The address multiplexing may need further changes. IORQ and MREQ get asserted at the point when the high order address byte is sent. For write this should be OK because the MWR cycle happens after the low byte has been sent, and thus ensures that anything qualified with \WR and \IORQ (or for memory \WR and \MREQ) won't glitch. On the read side however the processor drops MRD *before* the low address byte hits the bus. A glitched memory read is fine as by the time the device has sampled the data the correct address will have been present for some time. For I/O read with side effect however a read from $FFxx will read $FFFF momentarily. Hopefully not putting a device with side effects at I/O $FF is sufficient. However the bus cycles resulting don't look all that Z80 like but seem to work fine with everything tested except Z80 specific peripheral chips.
It should be possible to use an 1805 or 1806 with this board. That will result in VDD being fed from VCC on the 1806 and \ME being held high on the 1805