By whygee on Thursday 1 January 2009, 12:21 - VHDL
Hello and Happy New Year Everybody !
I took some time to work on the next major building block of the YASEP16 execution unit : the shift/rotate unit is now ready in 16-bit flavour.
I concentrate now on YASEP16 because it is smaller and marginally faster, and consumes less bandwidth. It can fit easily in the A3P250 and its 6K 3-input tiles, though i don't know how many tiles are needed in the end.
SHL_16 uses about 220 tiles, and Actel's place&route estimates the unit to run at 140MHz in pipelined version. This is slightly faster and smaller than ASU_ROP2 that performs Add/Sub and boolean operations (115 MHz and about 350 tiles). The overall ALU (ASU_ROP2 + SHL + IE) is going to take roughly 700 tiles, or 1/8th of the A3P250's surface. Speed is looking satisfying, as I intend to clock the thing at 96MHz on the ACME boards (64MHz * 1.5 with the PLL).
Overall, the following operations are ready for the 16-bit flavor :
- ASU : ADD, SUB and compares as side effects.
- ROP2 : AND/OR/XOR/NAND/NOR/XNOR/ANDN/ORN as well as comparison for equality (XOR followed by a OR reduction tree)
- SHL : SHR/SHL/ROR/ROL/SAR
The next part to be developped is the IE (Insert/Extract) unit, for the load and stores of bytes into a half-word. Stay tuned...
''Note : some P&R runs give a bit higher working frequencies but I
reserve 15 or 20% of margin, since I expect that all the units put together
will need even more MUX2 all over the place, longer wires etc. resulting in
slower operation.' Furthermore, it is only YASEP16 yet, and the 32-bit flavor
will double the design's size... '
I should have put the source code there as well as some schematics (just as I do with the YGREC8 now)