Working away on the software to make it easier to use the bubble board, and overall it is going well with completed routines to initialize the bubble, load parameters, read the boot loop, read the boot loop register, and write to the bubble. However, I am having trouble with an underflow error when reading the bubble
Using the bubble read command in poll mode, I can not figure out why my bubble memory board is letting me read past the initial FIFO load. I can write to the bubble and the 7220 FIFO status flag seems to be working fine (or possibly it is writing faster than I am filling). I can also read the boot loop and the boot loop register but those fit in the FIFO so the problem does not show up. The problem only seems to crop up when reading a page from the bubble and then only past the first FIFO load. Operating in polling mode with enable byte of 0x00, and the first FIFO load can be read without problems. Up to about byte 24, the status stays 81H as expected but a few bytes later the data turns to 00H as if reading past the FIFO but the status byte is still 81H. a few more byte reads and the status byte flips directly to 91H but the FIFO ready flag never goes to low as expected. After the full page read, the busy goes low and the status byte is now 30H so it is indicating a failed opcode and timing error as expected for a underflow error if reading past the FIFO load.
This has tied me up for most of the day. Anyone familiar enough to with the intel 7110 and 7220 bubble system to be able to give advice?
UPDATE - Much Ado About Nothing:
It took me another day to track this down but I am happy to report that everything now seems to be working and I can now reliably use the bubble board!
After starting to dig into the hardware, looking at the serial communication between the 7220 and the 7242 and many scope traces later, it turns out that the problem was not hardware related but there was simply an issue in my initialization routine. Mostly by accident I discovered that if I switched to the low-level command mode (which sends commands directly to the 7220 bubble interface and the 7242 preformatter) and sent the 11H code to reinitialize the 7220, then bubble reads would start working for the higher level commands in the finished code. I did not catch this in the quick-and-dirty code because it was limited to single FIFO reads out of "convenience". After that discovery, it was just a matter of tracking down the bug in the new code. In both cases I was setting up the parametric registers properly but in the finished code (that has error checking and reporting) I messed up a bit-mask for the status read and as a result the code was inadvertently skipping over a key step of the initialization. The funny thing is that this bug would only show up in the bubble read and then only when going past the first page of the FIFO. That is sort of an odd time for an initialization bug to show up and I became convinced that the 7110 was somehow having trouble rotating or duplicating onto the output track. So all is well that ends well and I learned a *lot* more about these chips in the last two days !!