To provide a monthly update at least, a short summary on the current development lane progress:

• Blackbox API considered frozen for an upcoming 0.1(after summer break) release
• Board supply package for ECP5 versa board 'in sync' with a frozen yosys .deb package
• More real life designs tested:
  • pyrv32 (RISC-V core) elements post-map co-simulation
  • Memory inference scenarios verified

The `@blackbox` interface had undergone some extensive experimenting. In short, there are several usage scenarios, not all of them completely elaborated:

• Automated inference of a vendor blackbox primitive (hard PLL, Serdes block, etc.)
• Integration with an external Verilog/VHDL module: Creating a black box stub
• Implementing a top level design ('virtual board') in several ways and configurations:
  • Simulation, Co-Simulation with external models
  • ... for different target architectures and boards

What is also going to not change for a while - so you can safely base on it for own development:

• Co-Simulation setups
• Hierarchy interface (although there are issues with the name mangling)
• extension classes: BulkSignal, GeneratorClass

Still under scrutiny:

• Tri-State interface signals: These are not yet 100% nailed down, but chances will be that they are only allowed in top level modules for synthesis.
• VHDL std_logic compatible signals that know also know 'U', 'X': They might possibly never make it into the official MyHDL tree and will be kept in a separate package.
• Latch support: Likely to end up as an error when trying to infer one.
• Memory inference: Likely to end up as Blackbox model library

Finally, what requires some attention at this point is the underlying (p)yosys API, so it might be time to build a testing pipeline to make sure the supporting pillars don't break away with future revisions.