• Current State

    Justus Fassl03/04/2021 at 17:24 0 comments

    The Simulator is usable for easy math programs and simple algorithms. I programmed a simple add program and the fibonacci program to demonstrate. It can also give simple ASCII output with a "Terminal". I now want to program the simulated CPU to support loading from and writing to any address in memory. With this I would be able to continue work on my already started native assembler for the simulator. Multicore is still also planned... I would be very happy if some of you guys give it a try on github, if you have any questions I'd be happy to answer them.

  • Decisions...

    Justus Fassl12/19/2020 at 10:21 0 comments

    I decided to not realize this project as a circuit. It will stay as a Software Project. The Simulator will be extended to support multicore design.

  • Researching and learning

    Justus Fassl07/26/2020 at 19:48 0 comments

    I now finished a first raw simulator. I am not quite happy with the overall design yet. I will research for some improvements for the architecture before continuing to design. Already have some improvement ideas but it takes more time.

  • Regarding the Image

    Justus Fassl07/02/2020 at 09:39 0 comments

    To get a better idea of what I have to  implement in code, I first created a rough design sketch in logisim.

    This does not show how the simulator will work nor how the theoretical function of the processor is.