Loading the Monitor into the FPGA ROM

A project log for Retro 68000 CPU in an FPGA

Making a Retrocomputer with a 68000 CPU in an FPGA 07/10/2020 at 11:270 Comments

The HEX file initialization in Quartus is not well behaved. When you make 8-bit ROMs it works fine. When you make a 16-bit wide ROM it doesn't load corrected. That seems to be because the HEX loader in Quartus sees the file addresses as the offset to the 16-bit value rather than the byte address. For this code it then loads the address for every 16-byte line but bumps down by 1 line and tries to load the next line.

The workaround is use the srecords utility to shift the address and save the result as an Altera MIF file. The steps are:

Shift ROM addresses for Quartus FPGA Tool


Shift the records down

[PATH_TO_SRECORD_UTILITIES]\srec_cat monitor.hex -Intel -o monitor.srec -Motorola
[PATH_TO_SRECORD_UTILITIES]\srec_cat monitor.srec -offset - -minimum-addr monitor.srec -o monitor.mif -Memory_Initialization_File 16
-- FFFF8000:
-- Generated automatically by srec_cat -o --mif
DEPTH = 8192;
WIDTH = 16;
0000: 0000 0800 0000 8008 4DF8 0C00 42AE 004A 422E 0048 422E 0049 6136 6100;
000E: 05D8 6100 044E 49FA 09D0 6164 207C 0000 C000 2010 0C80 524F 4D32 6604;
001C: 4EA8 0008 4E71 4E71 4287 6128 614C 6100 0080 6100 00BE 60F0 41F9 0001;

Teesside TS2 Monitor (TSBUG2) Commands

For TSBUG 2 Version 23.07.86

<address> is a hexadecimal number, e.g. FF0A Arguments in square brackets are optional.