TUTOR Loading S-Records Timeout

A project log for Retro 68000 CPU in an FPGA

Making a Retrocomputer with a 68000 CPU in an FPGA 07/10/2020 at 17:590 Comments

I tried to load a program using the S-Record loader built into the Tutor monitor using the LO command. The problem was that the board immediately timed out. The reason is TUTOR has a software loop which times out the load in 10 seconds and the FPGA CPU is much, much faster than the 8 MHz 68000 in the TS2.

The "real" 68000 chip took 4 clocks to access memory (if DTACK* is grounded). The VHDL core takes one clock at 25 Mhz. That's a scaling factor of 4 for the single clock time and 25/8 for the raw clock itself. Thus, the VHDL design runs 12.5 times as fast as the original design.

The timeout loop was easy to find in the LST file and it's in two places:

4490 9fe2 243C 0003   MOVE.L  #LTIME,%D2     | D2 = 5 SEC DEADMAN @ 8MHZ
4490      20C8 
4557 a06a 263C 0001   MOVE.L  #LTIME/2,%D3  | D3 = 2 1/2 SEC @ 8MHZ (CHARATER  TIMER)
4557      9064 

The address of the offsets in the .MIF file is shifted right by two since the MIF file is for 16-bit data. It was easy to manually edit the MIF file and fix the two locations. Also, the base address of 0x8000 needs to be subtracted.

Here's the locations I patched in the MIF file.

0FEA: 48E7 7090 6100 FCAA 2648 6100 FC92 243C 0033 20C8 614A 6704 615C 60F8;

1030: 671C 0C01 0020 6D14 1C81 263C 0011 9064 220E 928D 0C41 0050 6A02 528E;

 Here's what it looked like after the patch was installed:

009FE0    FC 92 24 3C 00 33 20 C8  61 4A 67 04 61 5C 60 F8

00A060    67 1C 0C 01 00 20 6D 14  1C 81 26 3C 00 11 90 64

The timeout is now about 4 seconds.