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GPIO - 19 Bits

A project log for Retro 68000 CPU in an FPGA

Making a Retrocomputer with a 68000 CPU in an FPGA

land-boards.comland-boards.com 02/24/2022 at 13:470 Comments

Added GPIO ports to FPGA design.

Features

Indirect Register

-- 0 DAT0 bits [2:0]
-- 1 DDR0 bits [2:0]
-- 2 DAT2 bits [7:0]
-- 3 DDR2 bits [7:0]
-- 4 DAT3 bits [7:0]
-- 5 DDR3 bits [7:0]

Data Direction Register Bits

-- 0 in the data direction register marks the bit as an output
-- 1 in the data direction register marks it as an input

After reset, GPIOADR=0, all DDR*=0 (output) all DAT*=0 (output low). 

Route to DB-25 on MultiComp in a Box design.

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