Close

Hardware / Memory Map

A project log for OSI SD Card Operating System (OSISDOS)

Ohio Scientific / UK101 SD Card based Operating System under Multicomp FPGA Computer

land-boards.comland-boards.com 07/16/2020 at 11:270 Comments

Hardware

Runs on Cyclone II EP2C5 Mini Dev Board using Land Boards EP2C5-DB card which adds:

Design is based on Multicomp UK101 FPGA project with Multicomp elements (both) by Grant Searle.

Adds High Speed SD card interface from mc1024 project.

Memory Map

Address RangeFunction
0x0000-0x9FFF40KB SRAM
(Contiguous space viewable from BASIC)
0xA000-0xBFFF8KB BASIC in ROM
0xC000-0xCFFFExternal SRAM (not viewable by BASIC)
0xD000-0xD3FF1KB Display RAM
0xD000-0xD7FF2KB Display RAM (Not used)
0xDC00-0xDFFFScanned Keyboard (PS/2 replaces)
0xE000-0xE000Banked SRAM
16 banks of 4 KB
0xF000-0xF001ACIA Serial port
0xF002-0xF003J6 I/O
0xF004-0xF005J8 I/O
0xF006LED
0xF010-0xF017SD Card Control/Status/Data Registers
0xF100-0xF7FFOSISDOS ROM
0xF800-0xFFFF2KB CEGMON ROM

SD Card Interface

SD Card addresses are:

AddressRegister
0xF010SDDATA - Read/write data
0xF011SDSTATUS - Read
SDCONTROL - Write
0xF012SDLBA0 - Write-only
0xF013SDLBA1 - Write-only
0xF014SDLBA2 - Write-only

From the SD Controller VHDL file comments:

For both SDSC and SDHC (high capacity) cards, the block size is 512 bytes 
(9-bit value) and the SDLBA registers select the block number. 
SDLBA2 is most significant, SDLBA0 is least significant.

For SDSC, the read/write address parameter is a 512-byte aligned byte address. 
ie, it has 9 low address bits explicitly set to 0. 
23 of the 24 programmable address bits select the 512-byte block.
This gives an address capacity of 2^23 * 512 = 4GB .. 
BUT maximum SDSC capacity is 2GByte.

To avoid the addressing differences between SD and SDHC cards, I am going to use SDHC cards. These are greater than 2 GB (typically 4 GB cards) but can be as large as 64 GB. Hard to imagine there's that many GB of OSI / UK101 code out there.

Discussions