The archive contains several tests, including some exhaustive fault injection scans. The scan algorithm ignores all the gates with fewer than 4 inputs because

• No-input gates are constants and are not really implemented in ASIC. Nothing more to say about it.
• 1-input gates can only be inverters or buffers and they amount to a wire: the logic value is propagated (even if inverted) but if the gate is altered, it then behaves like a fixed value (a no-input gate) which can be detected.

Let's consider a gate BUF ( input A, output B) with LUT2(0,1):

• altering bit 0 will flip the 1 to 0, giving the LUT(0,0) and working like a GND,

• altering bit 1 will flip the 0 to 1, giving the LUT(1,1) and working like a VCC.

So as long as the A input is toggled, the Y output will change (or not if there is a fault). This change is propagated by

• output ports, or
• gate sinks which will in turn toggle output ports.

In conclusion, only gates with 2 or more inputs need a "LUT bit flips" to check the circuit.

This is a stark contrast with verification methods from the 60's where logic was wired (often manually) and the connexions themselves were delicate. Any fault needed to be identified, located and fixed, so the automated systems focused on the observability of each wire, sometimes forcing the addition of extra "observability wires" to circuits.

This old method has been carried over to IC design but the needs have changed: we only need to know if a circuit works correctly, we don't care much about why or where is fails (except for batch reliability analysis) so there is no need to focus on the wires.

However, some inference algorithms are shared because we still have to determine 2 things:

• How to observe a gate's output
• How to force a gate's input to a given value

This is where things will be difficult.