Fixed Display RAM Accesses

A project log for 68K CPU with Frame Buffer on FPGA

Working with AMR's build and improvements to the TG68 FPGA project 01/17/2021 at 18:270 Comments

The rectangles code wasn't working correctly on the EP4 FPGA card. Luckily, I found the problem relatively easily. Required setting the rows and columns for the SDRAM part that is used on the card. In the C4BoardTopLevel file.

tg68tst : entity work.VirtualToplevel
  generic map (
    -- W9825C6KH-6 Winbond 4M X 4 Banks x 16 bits SDRAM
    -- 13 rows, 9 columns
    sdram_rows => 13,
    sdram_cols => 9,

 The same fix needs to be done for the Cyclone V card since it used the same SDRAM part.