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Improved ANSI Screen

A project log for OpenCores PDP-8 on FPGA

OpenCores PDP-8 on FPGA

land-boardscomland-boards.com 07/02/2021 at 09:490 Comments

Added subroutines for UART and VDU initialization to the IOP16 code. Also, added an ANSI screen clear command (0x0c). Here's a handy ANSI codes chart.  

Here's the IOP16 code (latest version is here).

000    START   0xA017    JSR    INITVDU         INITIALIZE THE VDU    
001            0xA01C    JSR    INITURT         INITIALIZE THE ACIA UART    
002            0xA014    JSR    CLRSCR          CLEAR THE SCREEN CMD    
003    LOOP    0xA006    JSR    KB2PDP          KEYBOARD TO PDP-8    
004            0xA00D    JSR    PDP2VDU         PDP-8 TO VGA    
005            0xE003    JMP    LOOP            LOOP FOREVER    
006    KB2PDP  0x6004    IOR    Reg0    IO_04   READ KBD STATUS    
007            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
008            0xC004    BEZ    NOKDBD          NO KBD DATA    
009            0x6105    IOR    Reg1    IO_05   READ KBD DATA    
00a            0x9180    ORI    Reg1    0X80    MARK PARITY    
00b            0x7101    IOW    Reg1    IO_01   WRITE TO UART DATA    
00c    NOKDBD  0xB000    RTS                    DONE KEYBOARD TO UART    
00d    PDP2VDU 0x6000    IOR    Reg0    IO_00   PDP-11 TO VDU    
00e            0x8001    ARI    Reg0    0X01    MASK RX DATA PRESENT BIT    
00f            0xC004    BEZ    NOPDPD          NO UART DATA    
010            0x6101    IOR    Reg1    IO_01   READ UART DATA    
011            0x817F    ARI    Reg1    0X7F    8 TO 7 BITS    
012            0x7103    IOW    Reg1    IO_03   WRITE OUT SCREEN    
013    NOPDPD  0xB000    RTS            DONE    UART TO VGA    
014    CLRSCR  0x200C    LRI    Reg0    0X0C    SCREEN CLEAR    
015            0x7003    IOW    Reg0    IO_03   WRITE OUT SCREEN    
016            0xB000    RTS                            
017    INITVDU 0x2003    LRI    Reg0    0X03    RESET TERMINAL COMMAND    
018            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
019            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
01a            0x7002    IOW    Reg0    IO_02   WRITE VDU CMD REG    
01b            0xB000    RTS                            
01c    INITURT 0x2003    LRI    Reg0    0X03    RESET UART COMMAND    
01d            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
01e            0x2020    LRI    Reg0    0X20    TX CTRLS RTS    
01f            0x7000    IOW    Reg0    IO_00   WRITE UART CMD REG    
020            0xB000    RTS                            

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