The goal of this project is to use this design in a 8-bit Retro-Computer application. To meet this goal the 32 pushbutton and 32 LEDs need to be mapped to the CPU design.
As an example of this mapping:
- Bottom row 8 LEDs are CPU D0-D7 (toggle pins)
- Next 2 rows up are CPU A0-A15 (toggle pins)
- The top row is control lines/status LEDs (debounced pushbuttons / settable LEDs)
Selection of the function of a particular pushbutton is relatively simple. The bottom 24 bits are toggle buttons. The top 28 buttons should create either single pulses for uses like Reset and toggle pins for uses like Run/Halt. This is done by having the panel VHDL file entity look like:
entity FrontPanel01 is port ( -- Clock and reset i_CLOCK_50 : in std_logic := '1'; i_n_reset : in std_logic := '1'; -- 32 LEDs(outs), 32 Pushbuttons (ins) i_FPLEDs : in std_logic_vector(31 downto 0); o_PBRaw : out std_logic_vector(31 downto 0); o_PBLatched : out std_logic_vector(31 downto 0); o_PBToggled : out std_logic_vector(31 downto 0); -- The key and LED on the FPGA card i_key1 : in std_logic := '1'; o_UsrLed : out std_logic := '1'; -- External I2C connections io_I2C_SCL : inout std_logic; io_I2C_SDA : inout std_logic := '1'; i_I2C_INTn : in std_logic := '1' ); end FrontPanel01;
The relevant signals are:
- o_PBRaw - The pushbuttons as polled (~ ever 1 mS)
- o_PBLatched - Debounced pushbuttons
- o_PBToggled - Toggled pushbuttons
Application Specific Example
For this VHDL code, this means removing the loopback at the top level or more specifically gating with other signals). If the CPU is running, the Data and LEDs should reflect the values on the CPU Data and address lines. If the CPU is halted, the pushbuttons should reflect the address that is being accessed from the front panel.
For an example which is closer to the application, I created a new branch with the bottom 24 lines looped back as toggled pins and the top 8 lines looped back as debounced lines. Also, cleaned up the top VHDL file to move down pushbutton handling one layer lower. This uses the same IOP16 code as the previous log (FP01_LOOP2).