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[001] Introduction

A project log for rj32

A 16-bit RISC CPU with 32 instructions built with Digital and verilog for an FPGA.

rj45rj45 07/12/2021 at 21:480 Comments

Jan 2, 2021

At this point I have been building rj16 and recording videos of it. rj16 is a pipelined 16-bit 5 stage RISC processor, built in Go (golang). It had 127 instructions planned and was largely inspired by the SH-2 and M*Core processors. It was a grandiose design of epic proportions.

But I realized allowing rampant feature creep was not the way to finish a project. Plus I got a craving to maybe one day build this CPU in discrete logic chips on PCBs. If I wanted to ever have any hope of that, I needed to scale down.

I also wanted to build an OS for this processor, and at the time I was having difficulty finding anything that could fit in 64 KB (an issue I have since resolved). So I decided 32-bits would be easier for that goal.

So, because all I had of rj16 was a simulator in Go, I decided to start from scratch building rj32, a 32-bit version of the processor. This would internally be a 16-bit processor (like the m68k), but with a 32-bit instruction set, and all operations would happen on pairs of 16-bit registers.

And this time I decided to actually publish the videos on youtube for the first time. I had been recording for a while but too chicken to actually put those videos out there. But I decided that needed to change.

So with that rj32 was born.

I decided to build it in Digital with the intention of having it run on an FPGA, and keep it simple enough that maybe one day I could implement it with discrete 7400 series logic chips. And the whole journey would be recorded on youtube. Here is the very first video:

Note: This was remastered after a couple weeks to be more concise and more appropriately represent the series as a whole

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