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68008 for RC2014

A work in progress 68008 card for RC2014 and BP80 busses

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This is a (still buggy) design for a 68008 card on the RC2014 bus. The current test card works but has a certain amount of wire and rework on it. The next version is untested.

68008-rc2014-v3.pdf

Snapshot of the schematic

Adobe Portable Document Format - 67.03 kB - 08/18/2021 at 20:38

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EtchedPixels wrote 04/13/2022 at 23:27 point

The memory card is able to respond within the first cycle. So according to several other board designs (and of course the famous newsletter) - dtack can be grounded.

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Keith wrote 04/12/2022 at 00:59 point

I think you need to ensure the !WR pulse ends before asserting !DATACK. The classic way to do this is to have !DS control a 74LS164 shift register. See this circuit:

https://cdn.hackaday.io/files/295311263454304/J061_cct.png

There is a full explanation of how it works in the manual. You should be able to generate the timing you want very easily.

https://hackaday.io/project/29531-stebus-io-prototyping-board

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