Schematic diagram for a generic push-pull transformer power stage.  Design of the power stage is outside the scope of the project.  This diagram explains the general concept and shows why the PWM waveform needs to be balanced.

The timing diagrams show PWM timing for 4%, 50% and 98% duty.  98% duty is probably the maximum safe duty.  Anything higher will risk cross-conduction and short the transformer primary.  The ON pulses are spaced by 180 degrees phase and the ON times are same for each phase.

If the PWM timing is not balanced, there will be net DC current in the transformer.  This will eventually increase and saturate the transformer core.  This won't hurt the transformer, but the primary inductance will decrease a large amount.  This increases current in the transistors and might destroy them.

Next up:  ATMEGA328P timers and PWM modes.