This is in fact a 2kB RAM, inside the FPGA. This is the very first peripheral that I have used for debugging the core. I have put the very first programs in this little memory. The tool “in system memory content editor” from ALTERA allow to read or write in real time, like a RAM/EPROM emulator. The content can also be written by the CPU, for debugging purpose.
I have made errors on this part, which is more complex than needed. But it works.
The CPU cannot handle interrupts. Therefore, I have integrated a small FIFO between the PS/2 and the CPU, so that the computer doesn’t miss any information from the PS2.
There is 1 flag to indicate that the FIFO contains unread data.
There is no real serial interface, but just a GPIO port : 2 bits inputs and 2 bits output.
The serial port is emulated in software via a bit-banging method. I have only coded the RX part (from PC to A2Z), for downloading content to A2Z.
The choice of bit-banging is questionable : it is very slow, and limits the baudrate to 56kbps. This is not reliable above.
Downloading a 1MB file at 56kbps is very very slow. I could have made 10 times faster with a hardware serial port.
The FPGA integrates an SPI master interface.
There is only 1 peripheral connected to this SPI : 16MB of Flash memory.
The configuration is fixed : 8 bits transfers, 12.5MHz.
There are 2 shift register, one for the MISO and one for MOSI. The address of this peripheral is the same for both reading and writing to the SPI, even if the registers are physically different. The goal is to reduce the instruction count, and to avoid switching the address.
Each write instruction to this address triggers a transaction of 8 bits, that involve both MOSI and MISO buffers. The MISO buffer is therefore also filled just after a transaction triggered by a write order to the MOSI buffer.