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The Design

A project log for NE555 Dice Inversion

A modern-day reimagining of the NE555/CD4017 electronic dice

TimTim 12/20/2021 at 22:260 Comments

Bringing the NE555 into the future also means using modern tools. We'll describe the functionality of the dice in VHDL and use PCBFlow to synthesize the digital description into an implementation based on NE555 logic.

At the same time this will also be the first "real life" test of NE555 logic, as the MCPU is a bit too complex and large to detect basic errors with the logic style.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--  1     2     
--  3  0  3
--  2     1

-- Encoding:
-- 001  1
-- 010  2
-- 011  1,2
-- 100  2,3
-- 101  1,2,3
-- 110  2,3,4

entity dice555 is
    port (clk:    in    std_logic;
          n_clk:    in    std_logic;
          dice: out std_logic_vector(3 downto 0)

    );
end;

architecture main of dice555 is
    signal  cnt:    unsigned(2 downto 0);
begin
     process (clk,n_clk)
    begin
        if rising_edge(clk) then
            if cnt < 6 then
                cnt <= cnt + 1;
            else
                cnt <= "001";
            end if;
        end if;
    end process;

-- drive inverted LEDs
dice(0) <= NOT cnt(0);
dice(1) <= '1' when (cnt = "001") else '0';
dice(2) <= NOT cnt(2);
dice(3) <= '0' when (cnt = "11X") else '1';

end;

The VHDL source of the dice is shown above. Basically it consists of a counter, counting from 1 to 6 and repeating, and an encoder for the dice pattern.

The encoder has 4 outputs, dice.0 to dice.3, which are assigned as in the picture above. The plan is to connect the LEDs from VCC to ground, to utilize the better driving capability of the lower side NPN. Therefore the pattern encoding is inverted.

Output after the synthesis step below. Around 21 NE555 are needed to implement the dice circuit.

   Number of cells:                 18
     ne_DFF                          3
     ne_NAND2                        7
     ne_NAND3                        2
     ne_NOT                          6

   Chip area for module '\main': 39.000000

Logic after synthesis:

And the spice output after techmapping to the NE555 logic library:
.SUBCKT main clk n_clk dice.0 dice.1 dice.2 dice.3
X0 cnt.0 dice.0 ne_NOT
X1 cnt.2 dice.2 ne_NOT
X2 cnt.1 1 ne_NOT
X3 cnt.2 cnt.1 dice.3 ne_NAND2
X4 cnt.0 dice.3 2 ne_NAND2
X5 dice.0 cnt.1 3 ne_NAND2
X6 dice.2 1 4 ne_NAND2
X7 dice.3 3 4 5 ne_NAND3
X8 5 6 ne_NOT
X9 cnt.0 1 7 ne_NAND2
X10 3 7 8 ne_NAND2
X11 dice.3 8 9 ne_NAND2
X12 9 10 ne_NOT
X13 cnt.0 dice.2 1 11 ne_NAND3
X14 11 dice.1 ne_NOT
X15 clk 6 cnt.2 ne_DFF
X16 clk 2 cnt.0 ne_DFF
X17 clk 10 cnt.1 ne_DFF
.ENDS main

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