Why build a replica of the Apollo Guidance Computer? I have always wanted to build a computer based on TTL chips ever since that college lab course that taught the use of TTL chips. During my career as a software developer I was fortunate enough to work on a project that used a real time operating system where I was able to understand the intricacies of the operating system. I wrote device drivers for hardware boards that were created in house as well as the infrastructure add-ons. That was my favorite work project. Modern software developers have become so abstracted from the hardware and operating systems that their code is typically platform independent.

I want to understand a historic computer's architecture, both hardware and software, and what better computer than the Apollo Guidance Computer. The AGC has a serious coolness factor because it landed men on the moon and it was the first computer to use integrated circuit chips, thus bridging the gap between computers made from vacuum tubes and modern computers. The original Block I AGC was built using 4,700 single 3-input NOR gate chips. NASA pushed the manufacturers to improve the integrated circuit technology and reliability by creating the first flat pack chip. The Block II version of the AGC used these flat chips that contained two 3-input NOR gates. The Block II version was built from 2826 dual 3-input NOR gates (RTL chips) along with 3325 diodes and core memory. NOR gates were used because they are the “universal” gate from which all other logic gates can be derived. It was cheaper and quicker to throw all the time and money into developing one reliable chip at the cost of having to use more chips.

The AGC was designed and built by MIT in the early 1960s. The only small size computers of the time were developed to guide ballistic missiles. MIT was designing guidance control systems for the Polaris submarine launched missile. The Block I version of the AGC had 24K of ROM, 1K of RAM and 11 instructions. The Block II version had 36K of ROM, 2K of RAM and 34 instructions. Block II was based on the Block I architecture. Both were 16-bit computers with a clock speed of 1.024 MHz.

At the time there was no light weight, simplistic computer interface technology appropriate for a space capsule. The astronauts, who were test pilots, wanted gauges and dials as they would find in an airplane. The AGC used a simple keyboard and numeric displays. This calculator style interface was the first of its kind. The Block I version only supported the Command Module and flew the unmanned missions up through Apollo 6 where the Block II flew all the manned missions. The Block II upgrade was required as it also needed to fly the Lunar Module.

The AGC was designed using technology that did not exist at that time. By the end of the Apollo era, computer technology had progressed to the point that the AGC was obsolete. Manufacturers had gone on to produce the TTL series of chips that are still available today. As with most government contracts, there was not enough time or money to completely redesign the AGC with this newer technology.

The AGC solved two very difficult problems for aircraft that did not exist or were in their infancy, a digital autopilot and digital fly-by-wire. Autopilots of the time were analog devices that were large and heavy with limited capabilities. The X-15 project was just starting to introduce this technology. After the Apollo missions were complete in 1975, a surplus AGC was retrofitted into a F-8 Crusader fighter jet to be the first fly-by-wire aircraft. The other ground breaking feature was the incorporation of the newly developed Kalman filter algorithm. This was one of the first applications of the Kalman filter which is now ubiquitous in spacecraft and missile implementations.

Add on top of all that the fact that this computer and its software had to execute flawlessly, yet could not be fully tested ahead of time before actually landing on the moon. There were incrementally more complex missions, but some of those were combined in the race to beat the Russians to the moon. As a result, a complex software simulator had to be built to test the system as best as possible on the ground. The document E-2475, A Comprehensive Digital Simulation for the Verification of Apollo Flight Software, describes this effort.

There was one AGC in the Command Module and one in the Lunar Module. Along with the AGCs, there were other more simplistic computers that performed specific functions such as the Launch Vehicle Digital Computer (LVDC) that guided the Saturn V during the initial launch phase. The AGC in most cases monitored the functions of the other computers and was capable of taking over the functionality if the other computer failed.

The design is derived from various documents that can be found on-line at https://www.ibiblio.org/apollo/Documents/.  The following is a list of some of the more important documents. R-393 is a good overview description of the Block I design. R-700 is a good overview description of the Block II design. The core document of how each instruction works from a hardware perspective is the Block II Machine Instructions manual. Without this document, this effort would probably not have been possible.

R-393.pdf → Logical Description for the Apollo Guidance Computer (AGC4)

E-2052.pdf → AGC4 Basic Training Manual

1689.pdf → AGC4 Memo #9 – Block II Instructions

R-700.pdf → Computer Subsystem

AGC Information Series, ISSUE 32 Block II Machine Instructions

The basic computer runs machine code instructions that are assembled with an assembler called the YUL. These instructions are 16-bit words that are brought into the computer and converted into one or more sub-sequences. Each sub-sequence runs within a single Memory Cycle Time (MCT). Each MCT consists of twelve timing pulses. Each timing pulse asserts zero to five control pulses. A control pulse directs the hardware to perform a single function. For example an RA control pulse which stands for Read register A will place the contents of the A register onto the write (data) bus. A timing pulse may consist of the RA and WB control pulses which would place the contents of the A register onto the write bus and then place the bus contents into register B. The Timing Pulse Generator is a state machine that cycles through the timing pulses. During each timing pulse, the Control Pulse Matrix asserts zero to five control pulses read from the matrix plus the control pulses required to perform memory functions.

The design of the updated Block II version of the AGC is based on the original Block I design. The modules described below came from the Block I design described in R-393. Once the Block I design was understood, the Block II differences described in R-700 were added. The main differences are in how memory is managed, the concept of channels, the instruction set expansion and other minor capabilities that were added and/or removed.

This is a list of the main modifications from Block I to Block II.

  1. The LP register was moved to just after the A register and renamed as the L register. This was to accommodate double precision operations.
  2. More fixed memory was added and expanded using the super-bank bit, from 24,576 words to 36,864 words.
  3. Erasable memory was doubled from 1,024 words to 2,048 words.
  4. The Bank register was broken out into the EB, FB and BB registers to increase the amount of memory that can be addressed.
  5. The SL editing register was replaced by the EDOP (Edit Opcode) register which shifts data right seven bits.
  6. The DSKY was modified slightly to include a STBY/PRO key.
  7. Interrupts were increased from 5 to 10.
  8. Counters were increased from 20 to 29.
  9. Interface registers were increased from 143 to 227 and moved from erasable memory into a channel mechanism. The channels have their own address space.
  10. Control Pulses were modified.
  11. The multiply and divide instructions were modified to reduce execution time.
  12. The parity generation and test are now automatic as they always need to occur.
  13. The read bus was removed.
  14. There are significantly more instructions and many more sub-sequences.

My take on this computer is that it is a real-time computer that was specifically designed for a given purpose, optimized for the task at hand. The Block I version was very primitive, whereas the Block II version became much more capable with only a slight increase in the chip count. The user interface is very primitive, yet functional. This DSKY did not need to be more robust as the astronauts were test pilots and preferred gauges and dials. Bottom line, this computer performed flawlessly, executing the most dangerous mission imaginable.

There are file major sections in developing this computer:

1) Read the documents and understand how the computer works.

2) Modify Ron's assembler so it outputs a Motorola S-Record format file.

3) Build a simulator that works at the hardware level.

4) Build hardware drawings and breadboard various pieces of the logic.

5) Build and test the actual hardware.