A project log for Apollo Guidance Computer

A running hardware implementation of the AGC, block II using TTL chips.

wglasfordwglasford 07/06/2022 at 23:470 Comments

I started wiring up the Memory sub-system board and realized quickly that I needed the display board to show the state of the various registers.  I first had to create a backplane to connect the boards into.  The backplane carries all the signals the display board requires.  The display functionality was not part of the original AGC.  This functionality is based on my simulator and what I needed to control the simulation.  The actual computer required data and control signals are routed via ribbon cables on top of the boards.

Here is the backplane.  Notice that I left room for an additional board, just in case.  I had to make all the  connector cables and slots universal so I could move the board under test to the back of the stack to have access  to the wire wrap pins for debugging purposes.

The display panel has LEDs grouped by register.  In the middle of the board is an array of sub-sequences showing which sub-sequence is being executed.  All of the controls that are available on the simulator are available here, including a row of 16 data/address input switches.  I chose to solder this board and the front board of the DSKY.  All remaining boards are wire wrap for easy modification when I make that inevitable mistake.

All the LEDs are wired up and tested.  I am working on the switch logic.  

Here are some of design notes that help understand the schematics.

The backplane is used to route all LED and switch lines between the logic boards and the display board. There are 338 connectors (169 * 2). If a NOT gate is required for the LED to show positive logic, then that is placed on the logic board.

The lines are laid out so that each of the three logic boards (CTL, MEM, PROC) do not have doubled up or overlapping pins. This way only one row of wire wrap terminals are required. It also strengthens the connection as more pins are anchoring the boards. The schematics use global labels to identify connections to the backplane due to the limitations of drawing real estate. The backplane connectors are shown on the interface drawings as single row connectors. The largest connector is 40 pins so multiple 40 pin connectors are required. The global labels on the hardware diagrams are numbered as per the list below.

The pin layouts identify two rows; A & B. The purpose column identifies the subsystem-module purpose with the number of connections in parenthesis. Note: The register and memory switch LSBs are the lower number, the higher number is the MSB. There are two unused pins every 25 pins due to the space required for the backplane ribbon cable connectors. The following tables shows the pin assignments.

Row A:

Pin #Purpose
1-16MEM-EFM: Memory Bus (1-16)
17-25MEM-ADR: S Monitor Bus (1-9)
28-30MEM-ADR: S Monitor Bus (10-12)
31-39MEM-ADR: Bank Monitor (9)
40-52MEM-ADR: Address Bus (1-13)
55-57MEM-ADR: Address Bus (14-16)
63MEM-ADR: GTR1777
69MEM-ADR: Examine Memory Pushbutton (1)
70MEM-ADR: Examine Next Pushbutton (1)
71MEM-EFM: Read/Write Switch (1)
72MEM-ADR: AGC/Manual Switch (1)
73MEM-ADR: Clear Parity Pushbutton (1)
74MEM-EFM: Load Memory Pushbutton (1)
75MEM-INT: RUPT3 Switch (1)
76MEM-INT: RUPT4 Switch (1)
77MEM-INT: RUPT5 Switch (1)
78MEM-PAR: PR_1-15 (1)
79CTL-MON: SA (1)
82-97MEM-MBF: G Monitor Bus (1-16)
98-106MEM-ADR: Memory Switches (1-9)
109-115MEM-ADR: Memory Switches (10-16)
116CTL-MON: BPEN (1)
117CTL-CLK: Clock Control: 1 MHz / Slow (1)
119CTL-CLK: CLK1 (1)
121CTL-MON: RUN – Exec. Mode (Run/Step) (1)
122CTL-MON: INST – Exec. Control (Instruction/Sequence) (1)
123CTL-MON: FLCK – Clock Mode (Run/Step) (1)
124CTL-MON: Master Reset Switch (1)
125CTL-MON: STEP – Exec. Step (1)
126CTL-MON: MCLK – Clock Step (1)
127CTL-MON: GENRST - Master Reset (1)
128CTL-MON: Scalar Enable (1)
129-133CTL-SEQ-SEQB: SQ(0-5) (1-5)
136CTL-SEQ-SEQB: SQ(0-5) (6)
138-140CTL-SEQ-SEQA: PRE-STG(1-3) (3)
141-143CTL-SEQ-SEQA: STG(1-3) (3)
144CTL-SEQ-SEQA: BR1 (1)
145CTL-SEQ-SEQA: BR2 (1)
146-151CTL-SEQ_DCD: Sub-Sequence Bus (6)
152-160CTL-TPG: TPG Decoded State (1-9)
163-169CTL-TPG: TPG Decoded State (10-16)

Row B:

Pin #Purpose
1-16PROC-ALU: X Monitor Bus (16)
17-25PROC-ALU: Y Monitor Bus (1-9)
28-34PROC-ALU: Y Monitor Bus (10-16)
35-50PROC-ALU: B Monitor Bus (16)
51-52PROC-ALU: U Monitor Bus (1-2)
55-68PROC-ALU: U Monitor Bus (3-16)
69-79PROC-CRG: A Monitor Bus (1-11)
82-86PROC-CRG: A Monitor Bus (12-16)
87-102PROC-CRG: L Monitor Bus (16)
103PROC-ALU: CI (1)
104CTL-SCL: F10x Switch (1)
105CTL-SCL: F13x Switch (1)
106CTL-SCL: F17x Switch (1)
110CTL-CLK: Clock Rate (1)
111CTL-SCL: F10x (1)
112CTL-SCL: F13x (1)
113CTL-SCL: F17x (1)
114-129PROC-CRG: Q Mon Bus (1-16)
130-133PROC-CRG: Z Mon Bus (1-4) – Used by MEM-ADR-ATS
136-147PROC-CRG: Z Mon Bus (5-16) – Used by MEM-ADR-ATS
149-151MEM-INT: Selected RUPT (3)
152-154MEM-INT: RUPT Latch (3)
155MEM-INT: IRQ (1)
156-159MEM-CNT: Plus In (4)
160MEM-CNT: Plus In Sync (1)
163-165MEM-CNT: Plus In Sync (2-4)
166-168MEM-CNT: Selected Counter (3)
169MEM-INT: INH (1)

The backplane has enough room in case another chip board is required. No reason to "cut" myself or the ribbon cables short. Here are pictures of the front and back of the board.

CPU Connectors: The J connectors contain the computer connections related to bus data and control pulses. They are designed in such a way that the three rear sub-system boards are interchangeable. This is due to the fact that the “board under test” is in the rear and is easily accessible. This is accomplished by having a connector for each of the slot's ribbon cables on the backplane even though they may not be used by that specific logic board. These connectors are located on the top of the boards. Only two of the ribbon cables extend to the DISP board. These are located on the side of the boards.

The top connections are positioned to the left of the boards. The order is J107, J101, J106, J105, J102 and J100. J107 starts one pin to the right of the edge and there are two unused pins between connectors so the connector cables can fit.

The following table is as summary of the connectors, how many pins, the purpose, the boards requiring the connection and the spares. The pin assignments are left to right for top pins and bottom to top for side assignments.

LabelPinsPurposeBoardsSpare Pins
J10040Control PulsesCTL, PROC, MEM0
J10116Write BusCTL, PROC, MEM, DISP0
J10220Control PulsesCTL, PROC0
J10316Control PulsesDSKY, CTL7
J10420Channel Bus, Control PulsesDSKY, PROC, MEM, DISP, CTL2
J10520LG Bus, Control PulsesPROC, MEM2
J10640Control PulsesCTL, MEM1
J10716Address, Control PulsesCTL, MEM5

The following lists each ribbon cable and its pin assignments.

J100: (40 pins) CTL, PROC, MEM

PinSignalFull Name
1WCHWrite Channel bus
2RCHRead Channel bus
3F10XF10 Scaler Oneshot timeout (1 = active)
4L2GDDirect write L to G
5G2LSDirect write G to L
6WQCWrite Q to Channel bus
7RQCRead Channel bus to Q
8A2XDirect write A to X
9WZWrite to Z Reg.
10WYDWrite Y Reg to Write Bus shifted right 1 bit
11WYWrite to Y Reg.
12WY12Write 12 bits to Y Reg.
13WQWrite to Q Reg.
14CLXCClear X reg if BR1 = 0
15WLCWrite L to Channel bus
16RLCRead L to Channel bus
17WLWrite to L Reg.
18WBWrite to B Reg.
19WALSWrite to A & L Reg.
20WAWrite to A Reg.
21L16Write Octal 100000 to L
22B15XSet bit 15 of X reg to 1
23R15Octal 15 to Write Bus
24RB1Octal 1 to Write Bus
25R6Octal 6 to Write Bus
26R1COctal 1 (1's Comp) to Write Bus
27RB2Octal 2 to Write Bus
28RZRead Z Reg.
29RURead U Reg.
30Z16Set bit 16 of Z register
31NEACONInhibit end-around carry
32Z15Set bit 15 of Z register
33RQRead Q Reg.
34RLRead L Reg.
35RCRead C Reg.
36GENRSTReset the system
37RBRead B Reg.
38RARead A Reg.
39RSTRTOctal 4000 to Write Bus
40CISet Carry In

J101: (16 pins) Write Bus

PinSignalFull Name
1W1Write Bus bit 1
2W2Write Bus bit 2
3W3Write Bus bit 3
4W4Write Bus bit 4
5W5Write Bus bit 5
6W6Write Bus bit 6
7W7Write Bus bit 7
8W8Write Bus bit 8
9W9Write Bus bit 9
10W10Write Bus bit 10
11W11Write Bus bit 11
12W12Write Bus bit 12
13W13Write Bus bit 13
14W14Write Bus bit 14
15W15Write Bus bit 15
16W16Write Bus bit 16

J102: (20 pins) CTL, PROC

PinSignalFull Name
1RUSRead U reg with sign bit
2PONEXClear X reg and set bit 0 to one
3PTWOXClear X reg and set bit 1 to two
4MONEXSet X reg to minus 1
5PIFLPrevent end-around carry on X reg if L bit 1 is set
6NEACOFClear prohibit end-around carry
7READ0Read channel bus
8RAND0Read channel bus, AND with A reg
9ROR0Read channel bus, OR with A reg
10RXOR0Read channel bus, XOR with A reg
11WRITE0Write to channel bus
12WAND0Write to channel bus, AND with A reg
13WOR0Write to channel bus, OR with A reg
14RL10BBRead ten bits of L
15U16U reg bit 16 value
16L15L reg bit 15 value
17CLK1Clock 1 (normally low)
18CLK2Clock 2 (normally low)
19L1L reg bit 1 value

J103: (16 pins) CTL, DSKY

>th >Pin

SignalFull Name
1CLK1Clock 1 Pulse
2CLK2Clock 2 Pulse
3GENRSTGeneral Reset
4STBYStandby (0 = AGC in STBY state)
5KBD1Read from Channel 15 (Keyboard)
6DISPWrite to Channel 10 (Display)
7INDCWrite to Channel 11 (Indicators)
10CLK3Clock 3 Pulse

J104: (20 pins) PROC, DSKY, MEM, DISP, CTL

PinSignalFull Name
1CH1Channel Bus bit 1
2CH2Channel Bus bit 2
3CH3Channel Bus bit 3
4CH4Channel Bus bit 4
5CH5Channel Bus bit 5
6CH6Channel Bus bit 6
7CH7Channel Bus bit 7
8CH8Channel Bus bit 8
9CH9Channel Bus bit 9
10CH10Channel Bus bit 10
11CH11Channel Bus bit 11
12CH12Channel Bus bit 12
13CH13Channel Bus bit 13
14CH14Channel Bus bit 14
15CH15Channel Bus bit 15
16KB_STRKeyboard Strobe (Key pressed) (to KEYRUPT)
17PARALMParity Alarm Routed from MEM via J105
18L2L reg bit 2 value

J105: (20 pins) MEM, PROC

PinSignalFull Name
1LG1L to G Bus bit 1
2LG2L to G Bus bit 2
3LG3L to G Bus bit 3
4LG4L to G Bus bit 4
5LG5L to G Bus bit 5
6LG6L to G Bus bit 6
7LG7L to G Bus bit 7
8LG8L to G Bus bit 8
9LG9L to G Bus bit 9
10LG10L to G Bus bit 10
11LG11L to G Bus bit 11
12LG12L to G Bus bit 12
13LG13L to G Bus bit 13
14LG14L to G Bus bit 14
15LG15L to G Bus bit 15
16LG16L to G Bus bit 16
17G1G Reg bit 1
18G16G Reg bit 16

J106: (40 pins) CTL, MEM

PinSignalFull Name
1WEWrite to Memory
2SBWGWrite Memory to G Reg.
3GENRSTGeneral Reset
4W23Write to SL
5W22Write to CYL
6W21Write to SR
7W20Write to CYR
8RSBRead Super-bit
9RRPARead RUPT Address
10WSWrite to S Reg.
11REBRead Erasable Bank
12RFBRead Fixed Bank
13WGWrite to G Reg, no reset
14RGRead G Reg.
15CLK1Clock 1 Pulse
16MCROSpecial Multiply pulse
18RPTRead RUPT Opcode
19KRPTKnockdown RUPT Priority
20CLK2Clock 2 Pulse
21RBBKRead Both Banks
22WEBWrite to Erasable Bank
23WFBWrite to Fixed Bank
24WBBWrite to Both Banks
25WTSMove data from pre-S to S registers.
26WSBWrite the Super-bank bit
27CLRPClear RPCell
28IRQInterrupt Request
31WPCTRWrite Priority Counter Sequence
32RSCTRead Counter Address
33WOVRWrite Overflow
34EQU3Address is Octal 3
35EQU4Address is Octal 4
36EQU6Address is Octal 6
37GMZG Reg is all zeros25-31 Spare
38GTR1777Address > 01777M
39GTR7Address > 07
40EQU17Address = 017

J107: (16 pins) MEM, CTL

>td >14

PinSignalFull Name
1AD1Address bit 1
2AD2Address bit 2
3AD3Address bit 3
4AD4Address bit 4
5AD5Address bit 5
6AD6Address bit 6
7AD7Address bit 7
8-12Spare (5)
GETBPDetermine if breakpoint has been reached
15ISRUPTIs an interrupt pending?
16runPINCRun the PINC sub-sequence

DSKY Connectors: The three DSKY boards require interconnections. Given the number of pins required, this board set requires two 40-pin connectors, two 16-pin connectors and one 10-pin connector. The board rows are 47 pins wide so there is plenty of room for the two 40-pin connectors edge mounted across the top. The first connector (J300) contains pins 1-40. The second connector (J301) contains pins 41-80. The third connector (J302) contains pins 81-96. The fourth connector (J303) contains pins 100-115. The fifth connector (J304) contains pins 116-125. There is also a need for power connectors between the boards so they can be separated.

The boards are numbered to ease the decoding. Board #1 is the front board with the keys and display. Board #2 is the middle board with all the display transistors. Board #3 is the main chip board. To better understand this, the first table is a summary of what connectors go between which boards. This is followed by the detailed pin assignments.

ConnectorFromToPinsSparesPin RangePurpose
J300Board #1Board #34020-40Keyboard/Indicators/Sign Drivers
J301Board #1Board #240041-80LED Bank Digits/LED Digit Enable
J302Board #1Board #210181-90LED Digit Enable
J303Board #2Board #3160100-115Data, Activates, Control
J304Board #2Board #3104116-125Activates
1Keyboard0 Key
2Keyboard1 Key
3Keyboard2 Key
4Keyboard3 Key
5Keyboard4 Key
6Keyboard5 Key
7Keyboard6 Key
8Keyboard7 Key
9Keyboard8 Key
10Keyboard9 Key
11KeyboardVERB Key
12KeyboardERR RST Key
13KeyboardKEY RLSE Key
14KeyboardPLUS Key
15KeyboardMINUS Key
16KeyboardENTER Key
17KeyboardCLEAR Key
18KeyboardNOUN Key
19KeyboardPROC Key
22IndicatorsComputer Activity
23IndicatorsKEY REL
24IndicatorsOPR ERR
26IndicatorsUplink Activity
30IndicatorsNO ATT
32IndicatorsGimbal Lock
35Sign Signals+R3S
36Sign Signals-R3S
37Sign Signals+R2S
38Sign Signals-R2S
39Sign Signals+R1S
40Sign Signals-R1S
41LED Bank DigitsS46
42LED Bank DigitsS47
43LED Bank DigitsS41
44LED Bank DigitsS42
45LED Bank DigitsS45
46LED Bank DigitsS44
47LED Bank DigitsS43
48LED Bank DigitsS32
49LED Bank DigitsS31
50LED Bank DigitsS36
51LED Bank DigitsS33
52LED Bank DigitsS37
53LED Bank DigitsS34
54LED Bank DigitsS35
55LED Bank DigitsS26
56LED Bank DigitsS27
57LED Bank DigitsS21
58LED Bank DigitsS22
59LED Bank DigitsS25
60LED Bank DigitsS24
61LED Bank DigitsS23
62LED Bank DigitsS12
63LED Bank DigitsS11
64LED Bank DigitsS16
65LED Bank DigitsS13
66LED Bank DigitsS17
67LED Bank DigitsS14
68LED Bank DigitsS15
69LED Digit EnableEN45
70LED Digit EnableEN35
71LED Digit EnableEN46
72LED Digit EnableEN36
73LED Digit EnableEN47
74LED Digit EnableEN37
75LED Digit EnableEN48
76LED Digit EnableEN11
77LED Digit EnableEN21
78LED Digit EnableEN12
79LED Digit EnableEN22
80LED Digit EnableEN13
81LED Digit EnableEN23
82LED Digit EnableEN14
83LED Digit EnableEN24
84LED Digit EnableEN15
85LED Digit EnableEN25
86LED Digit EnableENN16
87LED Digit EnableEN26
88LED Digit EnableEN17
89LED Digit EnableEN27
100Driver DataOUT0
101Driver DataOUT1
102Driver DataOUT2
103Driver DataOUT3
104Driver DataOUT4
105Driver DataOUT5
106Driver DataOUT6
107Driver DataOUT7
108Driver ControlSTBY
109Driver ControlOUTDAT